# US 12,181,974 B2 · Techniques for peripheral utilization metrics collection and reporting

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- Number: US 12,181,974 B2
- Document ID: US12181974B2
- Status: Granted
- Kind: B2
- Application number: 17/563,398
- Filed: 2021-12-28
- Published: 2023-03-30
- Granted: 2024-12-31
- Earliest claimed: 2021-09-22
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Veeramanikandan Raju; Sudhakar Surendran; Anand Kumar G
- Web page: https://patentgrep.com/patent/US12181974B2

## CPC

- G06F 11/1441: {Resetting or repowering}
- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 11/1417: {Boot up procedures}
- G06F 11/2205: {using arrangements specific to the hardware being tested}
- G06F 11/2247: {Verification or detection of system hardware configuration}
- G06F 11/2284: {by power-on test, e.g. power-on self test [POST]}
- G06F 11/26: Functional testing
- G06F 11/3051: {Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247)}
- G06F 11/3055: {Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16)}
- G06F 11/3423: {where the assessed time is active or idle time}
- G06F 11/349: {for interfaces, buses}
- G06F 11/3688: {for test execution, e.g. scheduling of test suites}
- G06F 13/1668: {Details of memory controller}
- G06F 13/409: {Mechanical coupling (back panels H05K7/1438)}
- G06F 21/107: {License processing; Key processing}
- G06F 21/602: {Providing cryptographic facilities or services}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

## Claims

### Claim 1

An electronic device comprising:
a non-transitory storage device;
a peripheral;
a processor configured to transmit a request to enable the peripheral;
a system counter configured to transmit a time value; and
a power reset manager module configured to:
receive the request to enable the peripheral;
store, in response to the received request, a value in a first memory to indicate that the peripheral was enabled;
remain the value in the first memory at a subsequent disablement of the peripheral;
receive an indication of a capture rate;
receive the time value;
determine a current set of enabled peripherals based on the capture rate and time value; and
store, in a second memory, the determined current set of enabled peripherals,
wherein the processor is further configured to copy contents of the first memory and contents of the second memory to the non-transitory storage device.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the first memory and the second memory comprise registers.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein the processor is configured to encrypt the value and the determined current set of enabled peripherals based on a public key.

### Claim 4 (depends on 3)

The electronic device of claim 3, wherein the encrypting is performed as a part of an update procedure, and wherein the processor is further configured to generate an output indicating that the peripheral was enabled as a part of the update procedure.

### Claim 5 (depends on 1)

The electronic device of claim 1, wherein the electronic device further comprises:
a crash recovery module configured to:
access the first memory to obtain information indicating which peripherals were enabled;
access the second memory to obtain the determined current set of enabled peripherals;
store the information indicating which peripherals were enabled and the determined current set of enabled peripherals to the non-transitory storage device; and
reset the electronic device.

### Claim 6 (depends on 5)

The electronic device of claim 5, wherein the power reset manager module and the crash recovery module remain powered during the reset.

### Claim 7

A method comprising:
receiving, at a power reset manager module of an electronic device, a request to enable a peripheral of an electronic circuit;
in response to receiving the request, storing, by the power reset manager module, in a first memory, a value to indicate that the peripheral was enabled, wherein the value is remained at a subsequent disablement of the peripheral;
receiving an indication of a capture rate;
receiving a time value;
determining a current set of enabled peripherals based on the capture rate and time value;
storing, in a second memory, the determined current set of enabled peripherals;
copying contents of the first memory and contents of the second memory to a non-transitory storage device; and
generating, based on the copied contents of the non-transitory storage device, an output indicating that the peripheral was enabled and the determined current set of enabled peripherals as a part of an update procedure.

### Claim 8 (depends on 7)

The method of claim 7, wherein the power reset manager module remains powered during reset of the electronic device.

### Claim 9 (depends on 7)

The method of claim 7, wherein storing the value indicating that the peripheral was enabled comprising storing the value indicating that the peripheral was enabled in a first register, and wherein storing the determined current set of enabled peripherals comprises storing the determined current set of enabled peripherals in a second register.

### Claim 10 (depends on 7)

The method of claim 7, further comprising encrypting the value and the determined current set of enabled peripherals based on a public key.

### Claim 11 (depends on 10)

The method of claim 10, wherein the encrypting is performed as a part of the update procedure.

### Claim 12 (depends on 7)

The method of claim 7, further comprising:
accessing the first memory to obtain information indicating which peripherals were enabled;
storing the information indicating which peripherals were enabled to the non-transitory storage device; and
resetting the electronic circuit.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
retrieving the information indicating which peripherals were enabled during a startup process; and
determining a set of peripherals to test during the startup process based on the retrieved information indicating which peripherals were enabled.

### Claim 14

A circuit comprising:
a power reset manager module configured to:
receive a request to enable a peripheral of an electronic circuit;
set, in response to the received request, a bit value in a first register to indicate that the peripheral was enabled;
keep the bit value set in the first register at a subsequent disablement of the peripheral;
receive an indication of a capture rate;
receive a time value;
determine a current set of enabled peripherals based on the capture rate and time value;
store, in a second register, the determined current set of enabled peripherals;
receive a request of contents of the first register and contents of the second register; and
provide the bit value of the first register and the determined current set of enabled peripherals of the second register in response to the request.

### Claim 15 (depends on 14)

The circuit of claim 14, wherein the power reset manager module remains powered during reset of the circuit.

### Claim 16 (depends on 14)

The circuit of claim 14, further comprising a processor, wherein the processor is configured to encrypt the bit value and the determined current set of enabled peripherals based on a public key.

### Claim 17 (depends on 16)

The circuit of claim 16, wherein the encrypting is performed as a part of an update procedure.

### Claim 18 (depends on 14)

The circuit of claim 14, wherein the power reset manager module is configured to provide the bit value as a part of a debug procedure, and provide the determined current set of enabled peripherals as a part of an update procedure or as a part of the debug procedure.

### Claim 19 (depends on 14)

The circuit of claim 14, further comprising a crash recovery module configured to:
access the first register to obtain information indicating which peripherals were enabled;
access the second register to obtain the determined current set of enabled peripherals;
store the information indicating which peripherals were enabled and the determined current set of enabled peripherals to a non-transitory storage device; and
generate a signal to reset the electronic circuit.