# US 12,181,966 B2 · Reduction of latency impact of on-die error checking and correction (ECC)

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- Number: US 12,181,966 B2
- Document ID: US12181966B2
- Status: Granted
- Kind: B2
- Application number: 17/225,777
- Filed: 2021-04-08
- Published: 2021-07-22
- Granted: 2024-12-31
- Earliest claimed: 2021-04-08
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Kuljit S. Bains; Narasimha Lanka
- Web page: https://patentgrep.com/patent/US12181966B2

## CPC

- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 11/0784: {Routing of error reports, e.g. with a specific transmission path or data flow}
- G06F 11/0787: {Storage of error reports, e.g. persistent data storage, storage using memory protection}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/106: {Correcting systematically all correctable errors, i.e. scrubbing}
- G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device stores the corrected data internally to the memory device. When an error is detected, the memory device provides an indication to the memory controller, which can then request the corrected data.

## Claims

### Claim 1

A memory device comprising:
a memory array;
a hardware interface to couple to a memory controller; and
error checking and correction (ECC) circuitry to receive read data from an address of the memory array in response to a read command from the memory controller, perform error checking on the read data, detect a severity of error in the read data, encode an indication of errors to indicate the severity of error including a selection among no errors, corrected error, and uncorrected error, return the indication of errors, return the read data without application of error correction, apply error correction to the read data, and store corrected read data internally to the memory device.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the ECC circuitry is to store the corrected read data in a buffer of the memory device.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the ECC circuitry is to store the corrected read data in a register accessible to the memory controller.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the indication comprises an indication of a correctable, uncorrected error in the read data.

### Claim 5 (depends on 4)

The memory device of claim 4, further comprising the hardware interface to receive a subsequent read command for the corrected read data, and return the corrected read data in response to the subsequent read command for the corrected read data.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein the read command for the corrected read data comprises a subsequent read command to the address of the memory array.

### Claim 7 (depends on 1)

The memory device of claim 1, further comprising:
a register to store an address of the read command, wherein in response to a subsequent read command with a subsequent address, and provide the corrected read data when the subsequent address and the stored address match.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate (DDR) standard.

### Claim 9

A memory controller comprising:
a hardware interface to couple to a memory device; and
command logic to generate a read command to an address of the memory device;
wherein in response to the read command, the hardware interface is to receive data from the address without application of on-die error correction by error checking and correction (ECC) circuitry of the memory device and an encoded indication of errors to indicate a severity of error in the data including a selection among no errors, corrected error, and uncorrected error; and
wherein in response to the indication of errors indicating a correctable, uncorrected error in the data, the command logic is to generate a subsequent read command to receive the data from the address with application of on-die error correction by the ECC circuitry of the memory device.

### Claim 10 (depends on 9)

The memory controller of claim 9, wherein the subsequent read command comprises a read command to the address.

### Claim 11 (depends on 9)

The memory controller of claim 9, wherein the subsequent read command comprises a read command to a register accessible by the memory controller.

### Claim 12 (depends on 9)

The memory controller of claim 9, wherein the hardware interface is to couple to multiple memory devices in parallel, and further comprising:
host ECC circuitry to perform error checking on data received from the multiple memory devices;
wherein the host ECC circuitry is to perform error correction for a single bit error (SBE) for data received from the multiple memory devices, and generate the subsequent read command to receive the data from the address with application of on-die error correction by the ECC circuitry of the memory devices in response to a multibit error (MBE) in the data received from the multiple memory devices.

### Claim 13

A system comprising:
a memory device including:
a memory array; and
error checking and correction (ECC) circuitry to receive read data from an address of the memory array, perform error checking on the read data, detect a severity of error in the read data, encode an indication of errors to indicate the severity of error including a selection among no errors, corrected error, and uncorrected error, return the indication of errors, return the read data without application of error correction, apply error correction to the read data, and store corrected read data internally to the memory device; and
a memory controller including:
command logic to generate a read command to the address of the memory device;
wherein in response to the read command, the memory device is to return the read data without application of error correction and the indication of errors.

### Claim 14 (depends on 13)

The system of claim 13, wherein the ECC circuitry is to store the corrected read data in a buffer of the memory device, or in a register accessible to the memory controller.

### Claim 15 (depends on 13)

The system of claim 13, wherein the indication comprises an indication of a correctable, uncorrected error in the read data.

### Claim 16 (depends on 13)

The system of claim 13, wherein the indication comprises an indication of a correctable, uncorrected error in the read data, wherein the memory controller is to send a subsequent read command for the corrected read data, the memory device to return the corrected read data in response to the subsequent read command for the corrected read data.

### Claim 17 (depends on 13)

The system of claim 13, the memory device further comprising:
a register to store an address of the read command, wherein in response to a subsequent read command with a subsequent address, and provide the corrected read data when the subsequent address and the stored address match.

### Claim 18 (depends on 13)

The system of claim 13, further comprising one or more of:
a host processor device coupled to the memory controller;
a display communicatively coupled to a host processor;
a network interface communicatively coupled to a host processor; or
a battery to power the system.