# US 12,181,958 B2 · Scalable architecture for error capturing with single logger approach for automotive systems

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- Number: US 12,181,958 B2
- Document ID: US12181958B2
- Status: Granted
- Kind: B2
- Application number: 18/145,925
- Filed: 2022-12-23
- Published: 2024-06-27
- Granted: 2024-12-31
- Earliest claimed: 2022-12-23
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Sateeshkumar Injarapu; Manish Kumar Saxena; Amit Duggal; Nitin Jaiswal
- Web page: https://patentgrep.com/patent/US12181958B2

## CPC

- G06F 11/0787: {Storage of error reports, e.g. persistent data storage, storage using memory protection}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F 11/07: Responding to the occurrence of a fault, e.g. fault tolerance
- G06F 11/0724: {in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80)}
- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 11/0781: {Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level}
- G06F 11/0784: {Routing of error reports, e.g. with a specific transmission path or data flow}
- G11C 29/26: Accessing multiple arrays (G11C29/24 takes precedence)
- G11C 29/4401: {for self repair}
- G11C 2029/0401: {in embedded memories}
- G11C 2029/0411: {Online error correction}
- G11C 2029/1206: {Location of test circuitry on chip or wafer}
- G11C 2029/1208: {Error catch memory}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Various embodiments include methods and devices for error capturing implemented in a computing device. Embodiments may include receiving a plurality of error data for a plurality of memories of a plurality of processors at an error logger, including an error data for a memory of a processor having an identification of at least one faulty bit of the memory. Embodiments may include receiving a plurality of requests from a plurality of error capture modules for the processor at an error selection module for the processor, and retrieving an error data from an error capture module by the error selection module in response to a request from the error capture module being ordered prior to another request from another error capture module. Embodiments may include sending the error data to the error logger, and storing the error data at the error logger in an order relative to another error data.

## Claims

### Claim 1

A method of error capturing implemented in a computing device, comprising:
receiving a plurality of error data for a plurality of memories of a plurality of processors at an error logger,
wherein the plurality of memories of the plurality of processors includes a first memory of a first processor and the plurality of error data includes a first error data for the first memory of the first processor including an identification of at least one faulty bit of the first memory.

### Claim 2 (depends on 1)

The method of claim 1, further comprising receiving the plurality of error data for the plurality of memories of the plurality of processors at a plurality of error capture modules including receiving the first error data at an error capture module of the plurality of error capture modules.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
receiving a plurality of requests from a plurality of error capture modules for the first processor at an error selection module for the first processor, wherein each of the plurality of requests is configured to indicate to the error selection module at least one error data of the plurality of error data is stored at an error capture module of the plurality of error capture modules; and
retrieving the first error data from a first error capture module of the plurality of error capture modules by the error selection module in response to a first request of the plurality of requests from the first error capture module having priority to a second request of the plurality of requests from a second error capture module of the plurality of error capture modules.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
sending the first error data to the error logger; and
storing the first error data at the error logger in an order relative to a stored error data of a memory of the plurality of memories of the plurality of processors, wherein the plurality of error data includes the stored error data.

### Claim 5 (depends on 3)

The method of claim 3, further comprising:
sending, from the error logger to the error selection module, a first acknowledgement signal configured to indicate receipt of the first error data; and
retrieving a second error data from the second error capture module by the error selection module in response to the second request and the first acknowledgement signal.

### Claim 6 (depends on 5)

The method of claim 5, wherein the second request has priority to a third request of the plurality of requests from a third error capture module of the plurality of error capture modules,
the method further comprising:
sending, from the error logger to the error selection module, a second acknowledgement signal configured to indicate receipt of the second error data; and
retrieving a third error data from the third error capture module by the error selection module in response to a third request and the second acknowledgement signal.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
receiving the first error data for the first memory of the first processor at the error logger, wherein the first error data includes an identification of a number of faulty bits;
generating a first interrupt signal configured as a single bit fault indicator in response to the identification of the number of faulty bits being one bit; and
generating a second interrupt signal configured as a double bit fault indicator in response to the identification of the number of faulty bits being two bits.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
receiving a third interrupt signal at a functional safety unit from the error logger;
generating a first safety signal by the functional safety unit in response to the third interrupt signal being the first interrupt signal; and
generating a second safety signal by the functional safety unit in response to the third interrupt signal being the second interrupt signal.

### Claim 9 (depends on 1)

The method of claim 1, wherein the plurality of error data is configured with information identifying at least one faulty bit-cell location of the memory that is faulty.

### Claim 10 (depends on 1)

The method of claim 1, wherein the error logger is a single error logger for the plurality of memories of the plurality of processors.

### Claim 11

A computing device, comprising:
a plurality of memories;
a plurality of processors coupled to the plurality of memories; and
an error logger coupled to the plurality of memories and configured to receive a plurality of error data for the plurality of memories of the plurality of processors at the error logger,
wherein the plurality of memories of the plurality of processors includes a first memory of a first processor and the plurality of error data includes a first error data for the first memory of the first processor including an identification of at least one faulty bit of the first memory.

### Claim 12 (depends on 11)

The computing device of claim 11, further comprising a plurality of error capture modules configured to receive the plurality of error data for the plurality of memories of the plurality of processors including receiving the first error data at an error capture module of the plurality of error capture modules.

### Claim 13 (depends on 12)

The computing device of claim 12, further comprising an error selection module for the first processor, wherein the error selection module is configured to:
receive a plurality of requests from the plurality of error capture modules for the first processor, wherein each of the plurality of requests is configured to indicate to the error selection module at least one error data of the plurality of error data is stored at an error capture module of the plurality of error capture modules; and
retrieve the first error data from a first error capture module of the plurality of error capture modules in response to a first request of the plurality of requests from the first error capture module having priority to a second request of the plurality of requests from a second error capture module of the plurality of error capture modules.

### Claim 14 (depends on 13)

The computing device of claim 13, wherein the error logger is further configured to:
store the first error data in an order relative to a stored error data of a memory of the plurality of memories of the plurality of processors, wherein the plurality of error data includes the stored error data.

### Claim 15 (depends on 13)

The computing device of claim 13, wherein:
the error logger is further configured to send to the error selection module a first acknowledgement signal configured to indicate receipt of the first error data; and
the error selection module is further configured to retrieve a second error data from the second error capture module in response to the second request and the first acknowledgement signal.

### Claim 16 (depends on 15)

The computing device of claim 15, wherein:
the second request has priority to a third request of the plurality of requests from a third error capture module of the plurality of error capture modules;
the error logger is further configured to send to the error selection module a second acknowledgement signal configured to indicate receipt of the second error data; and
the error selection module is further configured to retrieve a third error data from the third error capture module in response to a third request and the second acknowledgement signal.

### Claim 17 (depends on 11)

The computing device of claim 11, the error logger is further configured to:
receive the first error data for the first memory of the first processor, wherein the first error data includes an identification of a number of faulty bits;
generate a first interrupt signal configured as a single bit fault indicator in response to the identification of the number of faulty bits being one bit; and
generate a second interrupt signal configured as a double bit fault indicator in response to the identification of the number of faulty bits being two bits.

### Claim 18 (depends on 17)

The computing device of claim 17, further comprising a functional safety unit in communication with the error logger and configured to:
receive a third interrupt signal from the error logger;
generate a first safety signal unit in response to the third interrupt signal being the first interrupt signal; and
generate a second safety signal in response to the third interrupt signal being the second interrupt signal.

### Claim 19 (depends on 11)

The computing device of claim 11, wherein the plurality of error data is configured with information identifying at least one faulty bit-cell location of the memory that is faulty.

### Claim 20 (depends on 11)

The computing device of claim 11, wherein the error logger is a single error logger for the plurality of memories of the plurality of processors.

### Claim 21

A computing device, comprising:
a plurality of memories;
a plurality of processors coupled to the plurality of memories;
an error logger coupled to the plurality of memories; and
means for receiving a plurality of error data for the plurality of memories of the plurality of processors at the error logger,
wherein the plurality of memories of the plurality of processors includes a first memory of a first processor and the plurality of error data includes a first error data for the first memory of the first processor including an identification of at least one faulty bit of the first memory.

### Claim 22 (depends on 21)

The computing device of claim 21, further comprising:
a plurality of error capture modules; and
means for receiving the plurality of error data for the plurality of memories of the plurality of processors at the plurality of error capture modules including receiving the first error data at an error capture module of the plurality of error capture modules.

### Claim 23 (depends on 21)

The computing device of claim 21, further comprising:
a plurality of error capture modules;
an error selection module for the first processor;
means for receiving a plurality of requests from the plurality of error capture modules for the first processor at the error selection module for the first processor, wherein each of the plurality of requests is configured to indicate to the error selection module at least one error data of the plurality of error data is stored at an error capture module of the plurality of error capture modules; and
means for retrieving the first error data from a first error capture module of the plurality of error capture modules by the error selection module in response to a first request of the plurality of requests from the first error capture module having priority to a second request of the plurality of requests from a second error capture module of the plurality of error capture modules.

### Claim 24 (depends on 23)

The computing device of claim 23, further comprising:
means for sending the first error data to the error logger; and
means for storing the first error data at the error logger in an order relative to a stored error data of a memory of the plurality of memories of the plurality of processors, wherein the plurality of error data includes the stored error data.

### Claim 25 (depends on 23)

The computing device of claim 23, further comprising:
means for sending, from the error logger to the error selection module, a first acknowledgement signal configured to indicate receipt of the first error data; and
means for retrieving a second error data from the second error capture module by the error selection module in response to the second request and the first acknowledgement signal.

### Claim 26 (depends on 25)

The computing device of claim 25, wherein the second request has priority to a third request of the plurality of requests from a third error capture module of the plurality of error capture modules,
the computing device further comprising:
means for sending, from the error logger to the error selection module, a second acknowledgement signal configured to indicate receipt of the second error data; and
means for retrieving a third error data from the third error capture module by the error selection module in response to a third request and the second acknowledgement signal.

### Claim 27 (depends on 21)

The computing device of claim 21, further comprising:
means for receiving the first error data for the first memory of the first processor at the error logger, wherein the first error data includes an identification of a number of faulty bits;
means for generating a first interrupt signal configured as a single bit fault indicator in response to the identification of the number of faulty bits being one bit; and
means for generating a second interrupt signal configured as a double bit fault indicator in response to the identification of the number of faulty bits being two bits.

### Claim 28 (depends on 27)

The computing device of claim 27, further comprising:
a functional safety unit;
means for receiving a third interrupt signal at the functional safety unit from the error logger;
means for generating a first safety signal by the functional safety unit in response to the third interrupt signal being the first interrupt signal; and
means for generating a second safety signal by the functional safety unit in response to the third interrupt signal being the second interrupt signal.

### Claim 29 (depends on 21)

The computing device of claim 21, wherein:
the plurality of error data is configured with information identifying at least one faulty bit-cell location of the memory that is faulty; and
the error logger is a single error logger for the plurality of memories of the plurality of processors.

### Claim 30

A non-transitory processor-readable medium having stored thereon processor executable instructions configured to cause a processor of a computing device to perform operations comprising:
receiving a plurality of error data for a plurality of memories of a plurality of processors at an error logger,
wherein the plurality of memories of the plurality of processors includes a first memory of a first processor and the plurality of error data includes a first error data for the first memory of the first processor including an identification of at least one faulty bit of the first memory.