# US 12,181,953 B2 · Operating method of a nonvolatile memory device for programming multi-page data

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- Number: US 12,181,953 B2
- Document ID: US12181953B2
- Status: Granted
- Kind: B2
- Application number: 18/374,717
- Filed: 2023-09-29
- Published: 2024-01-18
- Granted: 2024-12-31
- Earliest claimed: 2020-08-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Wandong Kim; Jinyoung Kim; Sehwan Park; Hyun Seo; Sangwan Nam
- Web page: https://patentgrep.com/patent/US12181953B2

## CPC

- G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs}
- G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 16/34: Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C 29/025: {in signal lines}
- G11C 2029/0409: {Online test}
- G11C 2029/4002: {Comparison of products, i.e. test results of chips or with golden chip}
- G11C 2211/5623: Concurrent multilevel programming and reading
- G11C 2211/5644: Multilevel memory comprising counting devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

## Claims

### Claim 1

A nonvolatile memory device comprising:
a memory cell array including first memory cells connected to a word line adjacent to a selected word line and second memory cells connected to the selected word line;
a control logic circuit configured to program first page data among multi-page data, to the first memory cells; and
a page buffer unit configured to read previous page data previously stored in the second memory cells based on a first sensing value and a second sensing value, after programming the first page data,
wherein the control logic circuit is further configured to program the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein the control logic circuit is further configured to receive a program command with respect to the multi-page data, and program the first page data in response to the program command.

### Claim 3 (depends on 1)

The nonvolatile memory device of claim 1, further comprising:
a fail bit counter configured to calculate a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value,
wherein the control logic circuit is further configured to program the previous page data and the second page data to the second memory cells based on the first fail bit number.

### Claim 4 (depends on 1)

The nonvolatile memory device of claim 1, further comprising:
an input/output circuit configured to:
output the previous page data read from the second memory cells, and
receive previous correction page data generated by correcting an error of the read previous page data, and
wherein the control logic circuit is further configured to program the previous correction page data and the second page data to the second memory cells.

### Claim 5 (depends on 4)

The nonvolatile memory device of claim 4, wherein the input/output circuit is further configured to:
output a ready/busy signal in a ready state and a read fail flag,
receive a data output command with respect to the previous page data, after outputting the ready/busy signal and the read fail flag, and
output the read previous page data in response to the data output command.

### Claim 6 (depends on 4)

The nonvolatile memory device of claim 4, wherein the control logic circuit is further configured to receive a resume command, and program the previous correction page data and the second page data to the second memory cells in response to the resume command.

### Claim 7 (depends on 4)

The nonvolatile memory device of claim 4, wherein a ready/busy signal is maintained in a busy state while a program operation on the first page data, a read operation, and a program operation on the second page data are performed, and
the ready/busy signal indicates a ready state while a transmission operation of the previous page data, a reception operation of the previous correction page data, and a reception operation of the resume command are performed.

### Claim 8 (depends on 4)

The nonvolatile memory device of claim 4, wherein the input/output circuit is further configured to output state information indicating a program fail with respect to the multi-page data.

### Claim 9

A nonvolatile memory device comprising:
a memory cell array including memory cells connected to a selected word line;
an input/output circuit configured to receive first page data among multi-page data, and receive second page data among the multi-page data;
a control logic circuit configured to program the first page data to the memory cells; and
a page buffer unit configured to read the first page data stored in the memory cells based on a first sensing value and a second sensing value, after receiving the second page data,
wherein the control logic circuit is further configured to program the first page data read from the memory cells and the second page data to the memory cells.

### Claim 10 (depends on 9)

The nonvolatile memory device of claim 9, further comprising:
a fail bit counter configured to calculate a first fail hit number by comparing first hits of the first page data read based on the first sensing value to second bits of the first page data read based on the second sensing value,
wherein the control logic circuit is further configured to program the first page data read from the memory cells and the second page data to the memory cells based on the first fail bit number.

### Claim 11 (depends on 10)

The nonvolatile memory device of claim 10, wherein, when the first fail bit number is less than a first reference value, the second page data is programmed to the memory cells.

### Claim 12 (depends on 11)

The nonvolatile memory device of claim 11, wherein the input/output circuit is further configured to:
output the first page data read from the memory cells, when the first fail bit number is greater than or equal to the first reference value and less than a second reference value greater than the first reference value, and
receive first correction page data generated by correcting an error of the read first page data, and
wherein the control logic circuit is further configured to program the first correction page data and the second page data to the memory cells.

### Claim 13 (depends on 12)

The nonvolatile memory device of claim 12, wherein the input/output circuit is further configured to
output a ready/busy signal in a ready state and a read fail flag,
receive a data output command with respect to the first page data, after outputting the ready/busy signal and the read fail flag, and
output the read first page data in response to the data output command.

### Claim 14 (depends on 12)

The nonvolatile memory device of claim 12, wherein the control logic circuit is further configured to receive a resume command, and program the first correction page data and the second page data to the memory cells in response to the resume command.

### Claim 15 (depends on 12)

The nonvolatile memory device of claim 12, wherein the input/output circuit is further configured to output state information indicating a program fail with respect to the multi-page data, when the first fail bit number is greater than or equal to the second reference value.

### Claim 16

A nonvolatile memory device comprising:
a memory cell array including first memory cells connected to a word line adjacent to a selected word line and second memory cells connected to the selected word line;
a control logic circuit configured to program at least one page data among multi-page data, to the first memory cells; and
a page buffer unit configured to read at least one previous page data previously stored in the second memory cells based on a first read voltage and a second read voltage, after programming the at least one page data,
wherein the control logic circuit is further configured to program the at least one previous page data read from the second memory cells and remaining page data among the multi-page data to the second memory cells.

### Claim 17 (depends on 16)

The nonvolatile memory device of claim 16, wherein the control logic circuit is further configured to program the at least one previous page data read from the second memory cells and the remaining page data to the second memory cells, when a number of failing cells having a threshold voltage between the first read voltage and the second read voltage among the second memory cells is less than a reference value, and
wherein the nonvolatile memory device further comprises:
an input/output circuit configured to output state information indicating a program fail with respect to the multi-page data, when the number of failing cells is greater than or equal to the reference value.

### Claim 18 (depends on 17)

The nonvolatile memory device of claim 17, wherein the input/output circuit is further configured to:
output the at least one previous page data read from the second memory cells, and
receive at least one previous correction page data generated by correcting an error of the at least one previous data, and
wherein the control logic circuit is further configured to program the at least one previous correction page data and the remaining page data to the second memory cells.

### Claim 19 (depends on 18)

The nonvolatile; memory device of claim 18, wherein the input/output circuit is further configured to:
output a ready/busy signal in a ready state and a read fail flag,
receive a data output command with respect to the at least one previous data, after outputting the ready/busy signal and the read fail flag, and
output the at least one previous page data in response to the data output command.

### Claim 20 (depends on 18)

The nonvolatile memory device of claim 18, wherein the control logic circuit is further configured to receive a resume command, and program the previous correction page data and the remaining page data to the second memory cells in response to the resume command.