# US 12,181,952 B2 · Fence randomization with inter-chip fencing constraints > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,181,952 B2 - Document ID: US12181952B2 - Status: Granted - Kind: B2 - Application number: 17/977,017 - Filed: 2022-10-31 - Published: 2024-05-02 - Granted: 2024-12-31 - Earliest claimed: 2022-10-31 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Daniel Alexander Thorne; Kevin Calabrese - Web page: https://patentgrep.com/patent/US12181952B2 ## CPC - G06F 11/0721: {within a central processing unit [CPU]} - G06F 11/263: Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} - G06F 11/2002: {where interconnections or communication control functionality are redundant (flexible arrangements for bus networks involving redundancy H04L12/40176)} - G06F 11/1423: {by reconfiguration of paths} - G06F 11/1425: {by reconfiguration of node membership} - G06F 11/2025: {using centralised failover control functionality} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Fence randomization with inter-chip fencing constraints, including: receiving a fencing setup comprising one or more parameters for fencing a plurality of chips in a plurality of drawers; and selecting, based on the one or more parameters and one or more dependencies for implementing the one or more parameters, a subset of the plurality of chips for fencing, wherein the subset of the plurality of chips are selected at least partially randomly; generating a testing configuration indicating the selected subset of the plurality of chips. ## Claims ### Claim 1 A method of fence randomization with inter-chip fencing constraints, the method comprising: receiving a fencing setup comprising one or more parameters for fencing a plurality of chips in a plurality of drawers; selecting, based on the one or more parameters and one or more dependencies for implementing the one or more parameters, a subset of the plurality of chips for fencing, wherein the subset of the plurality of chips are selected at least partially randomly; generating a fencing configuration indicating the selected subset of the plurality of chips; and performing one or more test operations on only the selected subset of the plurality of chips based on the fencing configuration. ### Claim 2 (depends on 1) The method of claim 1, further comprising applying the fencing configuration to a system, wherein the one or more test operations are performed on the system, wherein generating the fencing configuration includes encoding data indicating the selected subset of the plurality of chips. ### Claim 3 (depends on 1) The method of claim 1, wherein the one or more parameters indicates a subset of the plurality of drawers for fencing, wherein the testing configuration further indicates the selected subset of the plurality of drawers. ### Claim 4 (depends on 3) The method of claim 3, wherein selecting the subset of the plurality of chips comprises selecting, for exclusion from the subset of the plurality of chips, one or more chips communicatively coupled to one or more unfenced drawers. ### Claim 5 (depends on 1) The method of claim 1, wherein the one or more parameters indicate one or more chips to be unfenced. ### Claim 6 (depends on 1) The method of claim 1, wherein the one or more parameters indicate one or more chip relationships to be represented in the fencing configuration. ### Claim 7 (depends on 1) The method of claim 1, wherein the one or more parameters indicate a minimum number of unfenced chips. ### Claim 8 (depends on 1) The method of claim 1, wherein the one or more parameters indicate a probability for randomly fencing one or more of the plurality of chips. ### Claim 9 An apparatus for fence randomization with inter-chip fencing constraints, the apparatus comprising a computer processor and computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of: receiving a fencing setup comprising one or more parameters for fencing a plurality of chips in a plurality of drawers; selecting, based on the one or more parameters and one or more dependencies for implementing the one or more parameters, a subset of the plurality of chips for fencing, wherein the subset of the plurality of chips are selected at least partially randomly; generating a fencing configuration indicating the selected subset of the plurality of chips; and performing one or more test operations on only the selected subset of the plurality of chips based on the fencing configuration. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the steps further comprise applying the fencing configuration to a system, wherein the one or more test operations are performed on the system, wherein generating the fencing configuration includes encoding data indicating the selected subset of the plurality of chips. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the one or more parameters indicates a subset of the plurality of drawers for fencing, wherein the testing configuration further indicates the selected subset of the plurality of drawers. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein selecting the subset of the plurality of chips comprises selecting, for exclusion from the subset of the plurality of chips, one or more chips communicatively coupled to one or more unfenced drawers. ### Claim 13 (depends on 9) The apparatus of claim 9, wherein the one or more parameters indicate one or more chips to be unfenced. ### Claim 14 (depends on 9) The apparatus of claim 9, wherein the one or more parameters indicate one or more chip relationships to be represented in the fencing configuration. ### Claim 15 (depends on 9) The apparatus of claim 9, wherein the one or more parameters indicate a minimum number of unfenced chips. ### Claim 16 (depends on 9) The apparatus of claim 9, wherein the one or more parameters indicate a probability for randomly fencing one or more of the plurality of chips. ### Claim 17 A computer program product for fence randomization with inter-chip fencing constraints, the computer program product comprising a non-transitory computer readable storage medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of: receiving a fencing setup comprising one or more parameters for fencing a plurality of chips in a plurality of drawers; selecting, based on the one or more parameters and one or more dependencies for implementing the one or more parameters, a subset of the plurality of chips for fencing, wherein the subset of the plurality of chips are selected at least partially randomly; generating a testing configuration indicating the selected subset of the plurality of chips; and performing one or more test operations on only the selected subset of the plurality of chips based on the fencing configuration. ### Claim 18 (depends on 17) The computer program product of claim 17, wherein the steps further comprise applying the fencing configuration to a system, wherein the one or more test operations are performed on the system, wherein generating the fencing configuration includes encoding data indicating the selected subset of the plurality of chips. ### Claim 19 (depends on 17) The computer program product of claim 17, wherein the one or more parameters indicates a subset of the plurality of drawers for fencing, wherein the testing configuration further indicates the selected subset of the plurality of drawers. ### Claim 20 (depends on 19) The computer program product of claim 19, wherein selecting the subset of the plurality of chips comprises selecting, for exclusion from the subset of the plurality of chips, one or more chips communicatively coupled to one or more unfenced drawers.