# US 12,181,913 B2 · Clock synchronization pulse width scaling > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,181,913 B2 - Document ID: US12181913B2 - Status: Granted - Kind: B2 - Application number: 17/562,216 - Filed: 2021-12-27 - Published: 2023-06-29 - Granted: 2024-12-31 - Earliest claimed: 2021-12-27 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Atul Ramakant Lele; Paul John Patchen; Ryan Alexander Smith; Bernd Hannes Schneider - Web page: https://patentgrep.com/patent/US12181913B2 ## CPC - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 1/10: Distribution of clock signals {, e.g. skew} - H03K 21/023: {comprising pulse shaping or differentiating circuits} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse. ## Claims ### Claim 1 An electronic circuit, comprising: an oscillator circuit configured to generate a first clock; a first divider circuit coupled to the oscillator circuit, and configured to divide the first clock by a first selectable divisor to generate a divided clock; a synchronization control circuit coupled to the oscillator circuit and the first divider circuit, and configured to generate a synchronization pulse; and a second divider circuit configured to divide the divided clock by a second selectable divisor, wherein the synchronization pulse synchronizes changes of the first and second selectable divisors, such that the first and second divider circuits are configured to change respectively a value of the first selectable divisor and a value of the second selectable divisor responsive to the synchronization pulse, and wherein a pulse width of the synchronization pulse that synchronizes the changes of the first and second selectable divisors corresponds to a period of the divided clock of the first divider circuit. ### Claim 2 (depends on 1) The electronic circuit of claim 1, further comprising: a power and clock manager circuit coupled to the first divider circuit and the second divider circuit, and configured to provide a new value of the first selectable divisor to the first divider circuit and provide a new value of the second selectable divisor to the second divider circuit at a predetermined time between consecutive activations of the synchronization pulse. ### Claim 3 (depends on 2) The electronic circuit of claim 2, wherein the power and clock manager circuit is configured to reduce a power supply voltage provided to the first divider circuit and the second divider circuit responsive to the value of the first selectable divisor being increased. ### Claim 4 (depends on 3) The electronic circuit of claim 3, wherein the power and clock manager circuit is configured to provide the new value of the first selectable divisor to the first divider circuit and the new value of the second selectable divisor to the second divider circuit prior to reduction of the power supply voltage provided to the first divider circuit and the second divider circuit. ### Claim 5 (depends on 1) The electronic circuit of claim 1, further comprising: a power and clock manager circuit coupled to the first divider circuit and the second divider circuit, and configured to increase a power supply voltage provided to the first divider circuit and the second divider circuit responsive to the value of the first selectable divisor being decreased. ### Claim 6 (depends on 5) The electronic circuit of claim 5, wherein the power and clock manager circuit is configured to provide a new value of the first selectable divisor to the first divider circuit and a new value of the second selectable divisor to the second divider circuit after increase of the power supply voltage provided to the first divider circuit and the second divider circuit. ### Claim 7 (depends on 1) The electronic circuit of claim 1, wherein: a trailing edge of the synchronization pulse corresponds to an end of a cycle of the divided clock; the cycle of the divided clock ends at an end of a predetermined number of cycles of the first clock; and a leading edge of the synchronization pulse corresponds to a start of the cycle of the divided clock. ### Claim 8 An electronic circuit, comprising: an oscillator circuit configured to generate a first clock; a first divider circuit coupled to the oscillator circuit, and configured to divide the first clock by a first selectable divisor to generate a divided clock; a peripheral circuit coupled to the first divider circuit, and comprising: a second divider circuit configured to divide the divided clock by a second selectable divisor; and a power and clock manager circuit coupled to the first divider circuit and the second divider circuit, and configured to: reduce a power supply voltage provided to the first divider circuit and the second divider circuit responsive to a new value of the first selectable divisor being greater than a current value of the first selectable divisor; and provide the new value of the first selectable divisor to the first divider circuit and a new value of the second selectable divisor to the second divider circuit prior to reduction of the power supply voltage provided to the first divider circuit and the second divider circuit. ### Claim 9 (depends on 8) The electronic circuit of claim 8, wherein the power and clock manager circuit is configured to increase the power supply voltage provided to the first divider circuit and the second divider circuit responsive to the new value of the first selectable divisor being less than the current value of the first selectable divisor. ### Claim 10 (depends on 9) The electronic circuit of claim 9, wherein the power and clock manager circuit is configured to provide the new value of the first selectable divisor to the first divider circuit and the new value of the second selectable divisor to the second divider circuit after increase of the power supply voltage provided to the first divider circuit and the second divider circuit. ### Claim 11 (depends on 8) The electronic circuit of claim 8, further comprising: a synchronization control circuit coupled to the oscillator circuit and the first divider circuit, and configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from the current value to the new value; wherein: a pulse width of the synchronization pulse is based on the current value of the first selectable divisor; and the second divider circuit is configured to replace a current value of the second selectable divisor with the new value of the second selectable divisor responsive to the synchronization pulse. ### Claim 12 (depends on 11) The electronic circuit of claim 11, wherein the pulse width of the synchronization pulse is equal to a period of the divided clock. ### Claim 13 (depends on 11) The electronic circuit of claim 11, wherein the power and clock manager circuit is configured to provide the new value of the first selectable divisor to the first divider circuit and provide the new value of the second selectable divisor to the second divider circuit at a predetermined time between consecutive activations of the synchronization pulse. ### Claim 14 A method, comprising: generating a first clock; dividing the first clock by a first selectable divisor to generate a divided clock; generating a synchronization pulse, wherein a pulse width of the synchronization pulse corresponds to a period of the divided clock; dividing the divided clock by a second selectable divisor; and changing a value of the first selectable divisor and a value of the second selectable divisor responsive to the synchronization pulse. ### Claim 15 (depends on 14) The method of claim 14, further comprising: providing a new value of the first selectable divisor to a first divider circuit and providing a new value of the second selectable divisor to a second divider circuit at a predetermined time between consecutive activations of the synchronization pulse. ### Claim 16 (depends on 15) The method of claim 15, further comprising: reducing a power supply voltage provided to the first divider circuit and the second divider circuit responsive to the value of the first selectable divisor being increased. ### Claim 17 (depends on 16) The method of claim 16, further comprising: providing the new value of the first selectable divisor to the first divider circuit and the new value of the second selectable divisor to the second divider circuit prior to reducing the power supply voltage provided to the first divider circuit and the second divider circuit. ### Claim 18 (depends on 15) The method of claim 15, further comprising: increasing a power supply voltage provided to the first divider circuit and the second divider circuit responsive to the value of the first selectable divisor being decreased; and providing the new value of the first selectable divisor to the first divider circuit and the new value of the second selectable divisor to the second divider circuit after increasing the power supply voltage provided to the first divider circuit and the second divider circuit.