# US 12,181,911 B2 · Automatic overclocking controller based on circuit delay measurement > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,181,911 B2 - Document ID: US12181911B2 - Status: Granted - Kind: B2 - Application number: 18/224,579 - Filed: 2023-07-21 - Published: 2024-07-11 - Granted: 2024-12-31 - Earliest claimed: 2023-01-06 - Assignees: Shanghaitech University - Applicants: Shanghaitech University - Inventors: Weixiong Jiang; Yajun Ha - Web page: https://patentgrep.com/patent/US12181911B2 ## CPC - G06F 1/08: Clock generators with changeable or programmable clock frequency - G05B 19/042: using digital processors (G05B19/05 takes precedence) - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - H04B 17/364: Delay profiles - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G) - H04B: TRANSMISSION - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract An automatic overclocking controller based on circuit delay measurement is provided, including a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller. Compared with the prior art, the present disclosure has following innovative points: A two-dimension-multi-frame fusion (2D-MFF) technology is used to process a sampling result, to eliminate sampling noise, and an automatic overclocking controller running on a heterogeneous field programmable gate array (FPGA) can automatically search for a highest frequency at which an accelerator can operate safely. ## Claims ### Claim 1 An automatic overclocking controller based on a circuit delay measurement, comprising a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller, wherein a phase of a shadow clock (SCLK) output by the clock generator is adjusted from 0° to 360°, the TDM controller controls a circuit delay detector to sample the clock generator N times in a same phase before moving to a next phase, until the clock generator is sampled in all phases, and a final sampling value of each phase of the all phases is an average value of sampling values obtained from N times of sampling in a current phase; the TDM controller is further configured to perform a horizontal multi-frame fusion on final sampling values of the all phases to obtain transition points θ1 and θ2; when the horizontal multi-frame fusion is performed, the final sampling value of each phase is defined as one frame of data; therefore, an nth frame of data obtained after the horizontal multi-frame fusion is an average value of an ( n - M - 1 2 ) t ⁢ h frame of data to an ( n + M - 1 2 ) t ⁢ h frame of data, wherein M represents a coefficient of the horizontal multi-frame fusion; the transition point θ1 is a point wherein a sampling value changes from 0 to 1 after the horizontal multi-frame fusion, and the transition point θ2 is a point wherein a sampling value changes from 1 to 0 after the horizontal multi-frame fusion; and the CPU is configured to obtain the transition points θ1 and θ2 from the TDM controller to calculate a circuit delay td, and determine a frequency fnext of an accelerator for a next operating cycle based on the circuit delay td. ### Claim 2 (depends on 1) The automatic overclocking controller based on the circuit delay measurement according to claim 1, wherein if the average value of the sampling values obtained from the N times of sampling in the current phase is not greater than 0.5, a final sampling value of the current phase is 0, and if the average value of the sampling values obtained from the N times of sampling in the current phase is greater than 0.5, a final sampling value of the current phase is 1. ### Claim 3 (depends on 1) The automatic overclocking controller based on the circuit delay measurement according to claim 1, wherein the TDM controller comprises a sampler and a transition point finder, wherein the sampler controls the circuit delay detector to obtain the final sampling values of the all phases and perform the horizontal multi-frame fusion, and the transition point finder searches for the transition points θ1 and θ2. ### Claim 4 (depends on 3) The automatic overclocking controller based on the circuit delay measurement according to claim 3, wherein the sampler shares a plurality of circuit delay detectors, and the CPU calculates a plurality of circuit delays td for a plurality of paths by using the plurality of circuit delay detectors, and selects a longest circuit delay td from the plurality of circuit delays td to determine the frequency fnext of the accelerator for the next operating cycle. ### Claim 5 (depends on 1) The automatic overclocking controller based on the circuit delay measurement according to claim 1, wherein the CPU calculates the circuit delay td according to a following formula: t d = θ 3 ⁢ 6 ⁢ 0 · T wherein θ = θ 1 + θ 2 + 180 ⁢ ° 2 , and T represents a clock cycle.