# US 12,181,910 B2 · Timing margin sensor

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- Number: US 12,181,910 B2
- Document ID: US12181910B2
- Status: Granted
- Kind: B2
- Application number: 18/104,233
- Filed: 2023-01-31
- Published: 2023-08-10
- Granted: 2024-12-31
- Earliest claimed: 2022-02-10
- Assignees: SambaNova Systems, Inc.
- Applicants: SambaNova Systems, Inc.
- Inventors: Mahmood Khayatzadeh; Satyajit Sarkar; Jinuk Shin
- Web page: https://patentgrep.com/patent/US12181910B2

## CPC

- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A timing margin sensor circuit includes one or more time-to-digital converters (TDCs), a predictor, and a translation circuit. The TDC(s) measure(s) progress of a clock signal through one or more chains of delay stages. The progress depends on sense conditions acting upon the delay chain, such as the supply voltage and the temperature. The predictor receives the measured progress. If the delay chain becomes slower, the predictor extrapolates a predicted progress value. If the delay chain becomes faster, the predictor outputs the actual progress value. The translator translates the predictor output value to sense information that can be used in a clock stretcher circuit. The timing margin sensor may further have an averager/selector to average or select from the results of multiple TDCs. The timing margin sensor may further have a calibrator to compensate for nominal sense conditions, and one or more tunable delays circuits.

## Claims

### Claim 1

A sensor circuit, comprising:
a first time-to-digital converter (the first TDC) with a first TDC clock input and a first TDC trigger input, wherein the first TDC includes a chain of delay stages sensitive to a sense condition;
a predictor coupled with an output of the first TDC and configured to output a worst of a predicted value and an actual value; and
a translation circuit with a first input coupled with an output of the predictor and with a data output coupled with an output of the sensor circuit.

### Claim 2 (depends on 1)

The sensor circuit of claim 1, further comprising:
a calibrator coupled with the output of the first TDC; and
a first variable delay circuit, coupled between a sensor circuit clock input and the first TDC clock input, and with a calibration input coupled with an output of the calibrator, wherein the first variable delay circuit delays an input clock signal with a delay time that depends on a calibrator output signal.

### Claim 3 (depends on 1)

The sensor circuit of claim 1, further comprising:
a divider coupled between a clock input of the sensor circuit and the first TDC clock input.

### Claim 4 (depends on 1)

The sensor circuit of claim 1, wherein the predictor outputs a predicted TDC output value when a current TDC output value is decreasing and to output the current TDC output value when the current TDC output value is increasing.

### Claim 5 (depends on 1)

The sensor circuit of claim 1, wherein the predictor has a prediction strength based on a level of the sense condition.

### Claim 6 (depends on 1)

The sensor circuit of claim 1, wherein the translation circuit receives a correction code on a second input.

### Claim 7 (depends on 1)

The sensor circuit of claim 1, wherein the translation circuit outputs one of a thermometer code and a binary number.

### Claim 8 (depends on 1)

The sensor circuit of claim 1, wherein the translation circuit comprises a lookup table.

### Claim 9 (depends on 1)

The sensor circuit of claim 1, wherein the translation circuit comprises and or more comparators, and wherein a comparator has an adjustable threshold.

### Claim 10 (depends on 1)

The sensor circuit of claim 1, further comprising:
a second TDC with a second TDC clock input and a second TDC trigger input; and
an averager/selector, with inputs coupled with the output of the first TDC and an output of the second TDC, and operable to average first TDC and second TDC output signals, and/or to select either an output signal of the first TDC or an output signal of the second TDC, wherein an output of the averager/selector is coupled with the predictor.

### Claim 11 (depends on 1)

The sensor circuit of claim 1, wherein the first TDC comprises:
a series of flipflops coupled with at least a part of the chain of delay stages, and with clock inputs coupled with the first TDC trigger input;
a noise removal circuit coupled with outputs of the flipflops, and operative to remove faulty flipflop output signals; and
an active flank detector circuit coupled with outputs of the noise removal circuit, having an output with an output signal that indicates a location of a detected active flank.

### Claim 12 (depends on 1)

The sensor circuit of claim 1, wherein:
the sense condition comprises at least one of a process corner, a supply voltage, a junction temperature, or a die temperature.

### Claim 13 (depends on 2)

The sensor circuit of claim 2, wherein the calibrator comprises:
a comparator to compare a target code with a calibrator input signal; and
a loop filter coupled between a subtractor output and the output of the calibrator.

### Claim 14 (depends on 13)

The sensor circuit of claim 13, wherein the comparator comprises a subtractor.

### Claim 15 (depends on 11)

The sensor circuit of claim 11, wherein:
the active flank detector circuit comprises a thermometer-to-binary converter.

### Claim 16 (depends on 14)

The sensor circuit of claim 14, further comprising:
a calibrator coupled with an output of the predictor;
a first variable delay circuit, coupled between a sensor circuit clock input and the first TDC clock input, and with a calibration input coupled with an output of the calibrator, wherein the first variable delay circuit delays an input clock signal with a first delay time that depends on a calibrator output signal; and
a second variable delay circuit, coupled between the sensor circuit clock input and a second TDC clock input, and with a calibration input coupled with an output of the calibrator, wherein the second variable delay circuit delays an input clock signal with a second delay time that depends on the calibrator output signal.

### Claim 17 (depends on 14)

The sensor circuit of claim 14, wherein:
the second variable delay circuit delays an inverted input clock signal with the second delay time that depends on the calibrator output signal.