# US 12,181,903 B2 · Power supply rejection enhancer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,181,903 B2 - Document ID: US12181903B2 - Status: Granted - Kind: B2 - Application number: 18/315,402 - Filed: 2023-05-10 - Published: 2023-09-07 - Granted: 2024-12-31 - Earliest claimed: 2021-03-25 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Kuan Chuang Koay; Hua Guan; Jize Jiang - Web page: https://patentgrep.com/patent/US12181903B2 ## CPC - G05F 1/56: using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) - G05F 1/565: sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) - H03F 3/16: with field-effect devices - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H03F: AMPLIFIERS ## Abstract In certain aspects, a system includes an amplifying circuit having an input and an output, a high-pass filter coupled between a gate of a pass transistor of a low dropout (LDO) regulator and the input of the amplifying circuit, and a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the gate of the pass transistor. ## Claims ### Claim 1 A system, comprising: an amplifying circuit having an input and an output; a high-pass filter coupled between a gate of a pass transistor of a low dropout (LDO) regulator and the input of the amplifying circuit, wherein the high-pass filter comprises a capacitor coupled between the gate of the pass transistor and the input of the amplifying circuit, and a resistor coupled to the input of the amplifying circuit, wherein the resistor is coupled between the input of the amplifying circuit and a drain of the pass transistor; and a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the gate of the pass transistor. ### Claim 2 (depends on 1) The system of claim 1, wherein the input of the amplifying circuit is coupled between the capacitor and the resistor. ### Claim 3 (depends on 1) The system of claim 1, wherein the resistor is coupled between the input of the amplifying circuit and an output of the LDO regulator. ### Claim 4 (depends on 3) The system of claim 3, wherein the input of the amplifying circuit is coupled between the capacitor and the resistor. ### Claim 5 (depends on 1) The system of claim 1, wherein the MOS capacitor comprises a metal-oxide-semiconductor (MOS) transistor having a gate coupled to the input of the amplifying circuit, and a drain and a source coupled to the output of the amplifying circuit. ### Claim 6 (depends on 5) The system of claim 5, wherein the pass transistor and the MOS transistor are of a same transistor type. ### Claim 7 (depends on 5) The system of claim 5, wherein the pass transistor comprises a first p-type metal-oxide-semiconductor (PMOS) transistor and the MOS transistor comprises a second PMOS transistor. ### Claim 8 (depends on 5) The system of claim 5, wherein the pass transistor comprises a first n-type metal-oxide-semiconductor (NMOS) transistor and the MOS transistor comprises a second NMOS transistor. ### Claim 9 (depends on 5) The system of claim 5, wherein a gate width or a gate area of the pass transistor is a multiple of a gate width or a gate area of the MOS transistor. ### Claim 10 (depends on 1) The system of claim 1, wherein the amplifying circuit comprises: an amplifier having a first input, a second input, and an output, wherein the output of the amplifier is coupled to the output of the amplifying circuit and the first input of the amplifier is coupled to the input of the amplifying circuit; a first resistor coupled to the second input of the amplifier; and a second resistor coupled between the output of the amplifier and the second input of the amplifier. ### Claim 11 (depends on 10) The system of claim 10, wherein the high-pass filter comprises: a capacitor coupled between the gate of the pass transistor and the input of the amplifying circuit; and a third resistor coupled to the input of the amplifying circuit. ### Claim 12 (depends on 11) The system of claim 11, wherein the third resistor is coupled between the input of the amplifying circuit and an output of the LDO regulator. ### Claim 13 (depends on 12) The system of claim 12, wherein the input of the amplifying circuit is coupled between the capacitor and the third resistor. ### Claim 14 (depends on 11) The system of claim 11, wherein the first resistor is coupled between the second input of the amplifier and an output of the LDO regulator. ### Claim 15 A system, comprising: an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator, a source of the pass transistor is coupled to a supply rail, and a drain of the pass transistor is coupled to an output of the LDO regulator, wherein the amplifying circuit comprises an amplifier having a first input, a second input, and an output, wherein the output of the amplifier is coupled to the output of the amplifying circuit and the first input of the amplifier is coupled to the input of the amplifying circuit, a first resistor coupled between the second input of the amplifier and the output of the LDO regulator, and a second resistor coupled between the output of the amplifier and the second input of the amplifier; a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the gate of the pass transistor; and a current-sensing transistor having a gate coupled to the gate of the pass transistor, a source coupled to the supply rail, and a drain coupled to the amplifying circuit. ### Claim 16 (depends on 15) The system of claim 15, wherein the pass transistor comprises a first p-type metal-oxide-semiconductor (PMOS) transistor and the current-sensing transistor comprises a second PMOS transistor. ### Claim 17 (depends on 15) The system of claim 15, wherein the MOS capacitor comprises a metal-oxide-semiconductor (MOS) transistor having a gate coupled to the input of the amplifying circuit, and a drain and a source coupled to the output of the amplifying circuit. ### Claim 18 (depends on 15) The system of claim 15, wherein the current-sensing transistors provides the amplifying circuit with a bias current for biasing the amplifying circuit. ### Claim 19 (depends on 15) The system of claim 15, wherein the amplifier comprises: a first input transistor having a gate coupled to the first input of the amplifier; a second input transistor having a gate coupled to the second input of the amplifier; a load circuit coupled to a drain of the first input transistor, a drain of the second input transistor, and the output of the amplifier; and a current mirror coupled to a source of the first input transistor, a source of the second input transistor, and the drain of the current-sensing transistor. ### Claim 20 (depends on 19) The system of claim 19, wherein a first terminal of the current mirror is coupled to the drain of the current-sensing transistor, and a second terminal of the current mirror is coupled to the source of the first input transistor and the source of the second input transistor. ### Claim 21 (depends on 20) The system of claim 20, wherein the current mirror is configured to mirror a current flowing into the first terminal of the current mirror at the second terminal of the current mirror.