# US 12,181,522 B2 · Integrated circuit having test circuitry for memory sub-systems

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- Number: US 12,181,522 B2
- Document ID: US12181522B2
- Status: Granted
- Kind: B2
- Application number: 18/049,775
- Filed: 2022-10-26
- Published: 2024-05-02
- Granted: 2024-12-31
- Earliest claimed: 2022-10-26
- Assignees: NXP USA, Inc.
- Applicants: NXP USA, Inc.
- Inventors: Alexander Hoefler; Jeffrey Stump
- Web page: https://patentgrep.com/patent/US12181522B2

## CPC

- G01R 31/318541: {Scan latches or cell details}
- G01R 31/31722: {Addressing or selecting of test units, e.g. transmission protocols for selecting test units (for scan test G01R31/318558)}
- G01R 31/318558: {Addressing or selecting of subparts of the device under test}
- G11C 7/106: {Data output latches}
- G11C 7/1087: {Data input latches}
- G11C 29/32: Serial access; Scan testing
- G11C 2029/0401: {in embedded memories}
- G11C 2029/3202: {Scan chain}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A system includes test control circuitry and a memory. The memory includes a memory array, a pre-decode circuit, and a plurality of address latches. Each address latch of the plurality of address latches is configured to operate in a scan chain of a plurality of scan chains for scan testing. A first set of the plurality of address latches each has a data input coupled to a corresponding address pin of the first memory and each has an output coupled to the pre-decode circuit. A second set of the plurality of address latches, mutually exclusive of the first set, each has a data input coupled to a data input of at least one latch in the first set of the plurality of latches and each is configured to not provide any input to the pre-decode circuit.

## Claims

### Claim 1

A system, comprising:
test control circuitry; and
a first memory comprising:
a memory array;
a pre-decode circuit; and
a plurality of address latches, each configured to operate in a scan chain of a plurality of scan chains for scan testing, wherein:
a first set of the plurality of address latches each has a data input coupled to a corresponding address pin of the first memory, each has a scan input, and each has an output coupled to the pre-decode circuit, and
a second set of the plurality of address latches each has a data input coupled to a data input of at least one latch in the first set of the plurality of latches, each has a scan input, and each is configured to not provide any input to the pre-decode circuit, wherein no address latch of the first set is in the second set and no address latch of the second set is in the first set.

### Claim 2 (depends on 1)

The system of claim 1, wherein the output of each latch of the plurality of address latches is coupled to a scan input of a subsequent latch of the plurality of address latches in a corresponding scan chain.

### Claim 3 (depends on 2)

The system of claim 2, wherein a total number of address pins of the first memory is less than a total number of address latches of the plurality of address latches.

### Claim 4 (depends on 3)

The system of claim 3, wherein the total number of address pins of the first memory is equal to a total number of address latches in the first set of the plurality of address latches.

### Claim 5 (depends on 2)

The system of claim 2, wherein the output of each latch of the plurality of address latches is coupled to the scan input of the subsequent latch of the plurality of address latches in the corresponding scan chain via a corresponding buffer.

### Claim 6 (depends on 1)

The system of claim 1, wherein the pre-decode circuit is configured to provide a plurality of pre-decoded address lines to the memory array, wherein the pre-decoded address lines address a selected storage location within the memory array.

### Claim 7 (depends on 6)

The system of claim 6, wherein the pre-decode circuit is coupled to receive a plurality of inputs, each input of a first set of the plurality of inputs corresponding to a latch of the first set of the plurality of address latches and each input of a second set of the plurality of inputs corresponding to a latch of the second set of the plurality of address latches, wherein each input of the first set of the plurality of inputs is coupled to an output from a corresponding latch of the first set of the plurality of address latches, and each input of the second set of the plurality of inputs, mutually exclusive of the first set of the plurality of inputs, is coupled to receive a fixed predetermined voltage.

### Claim 8 (depends on 7)

The system of claim 7, wherein each input of the second set of the plurality of inputs is coupled to a voltage supply terminal.

### Claim 9 (depends on 1)

The system of claim 1, wherein the test control circuitry is configured to provide test patterns to the plurality of scan chains during a shift phase of the scan testing, enable a capture phase of the scan testing, and receive test results from the plurality of scan chains during the shift phase of the scan testing.

### Claim 10

A system, comprising:
test control circuitry configured to perform scan testing of a plurality of scan chains;
a first compiled memory of a first size generated by a memory compiler, the first compiled memory comprising:
a first memory array;
a first pre-decode circuit; and
a first plurality of latches, each configured to operate as part of the plurality of scan chains, wherein each latch of the first plurality of latches has, in addition to a scan input, a data input coupled to a corresponding pin of the first memory and an output coupled to the first pre-decode circuit; and
a second compiled memory of a second size, smaller than the first size, generated by the memory compiler, the second compiled memory comprising:
a second memory array;
a second pre-decode circuit; and
a second plurality of address latches, each configured to operate as part of the plurality of scan chains, wherein:
a first set of the second plurality of latches each has a data input coupled to a corresponding pin of the second compiled memory, each has a scan input, and each has an output coupled to the second pre-decode circuit, and
a second set of the second plurality of latches each has a data input coupled to a data input of at least one latch in the first set of the second plurality of latches, each has a scan input, and each is configured to provide no input to the second pre-decode circuit, wherein no latch of the first set is in the second set and no latch of the second set is in the first set.

### Claim 11 (depends on 10)

The memory system of claim 10, wherein the output of each latch of the first and second plurality of latches is coupled to a scan input of a subsequent latch in a corresponding scan chain.

### Claim 12 (depends on 11)

The memory system of claim 11, wherein at least one scan chain of the plurality of scan chains spans both the first and second compiled memories.

### Claim 13 (depends on 10)

The memory system of claim 10, wherein the second compiled memory does not include any pins which are coupled to data inputs of the second set of the second plurality of latches without also being coupled to at least one data input of the first set of the second plurality of latches.

### Claim 14 (depends on 13)

The memory system of claim 13, wherein a total number of latches of the first plurality of latches equals a total number of latches of the second plurality of latches, but a total number of pins of the second compiled memory is less than a total number of pins of the first compiled memory.

### Claim 15 (depends on 14)

The memory system of claim 14, wherein each latch of the first and second plurality of latches is characterized as an address latch and each corresponding pin of the first compiled memory and the second compiled memory is characterized as an address pin.

### Claim 16 (depends on 15)

The system of claim 15, wherein:
the first pre-decode circuit is configured to provide outputs of the first plurality of latches as a first plurality of pre-decoded address lines to the first memory array, wherein the first plurality of pre-decoded address lines address a selected storage location within the first memory array, and
the second pre-decode circuit is configured to provide a second plurality of pre-decoded address lines to the memory array, wherein the second plurality of pre-decoded address lines address a selected storage location within the second memory array, wherein a total number of bits of the first plurality of pre-decoded address lines which address the selected storage location within the first memory array is greater than a total number of bits of the second plurality of pre-decoded address lines which address the selected storage location with in the second memory array.

### Claim 17 (depends on 16)

The system of claim 16, wherein:
the first pre-decode circuit is coupled to receive a first plurality of inputs, each coupled to an output of a corresponding latch of the first plurality of latches, and
the second pre-decode circuit is coupled to receive a second plurality of inputs, each input of a first set of the second plurality of inputs corresponding to a latch of the first set of the second plurality of latches and each input of a second set of the second plurality of inputs corresponding to a latch of the second set of the second plurality of inputs, wherein each input of the first set of the second plurality of inputs is coupled to an output from a corresponding latch of the first set of the second plurality of address latches, and each input of the second set of the second plurality of inputs is coupled to receive a voltage supply terminal.

### Claim 18 (depends on 15)

The system of claim 15, wherein the data input of each latch of the second set of the second plurality of latches is coupled to a shared pin of the second compiled memory which is also coupled to a data input of a latch in the first set of the second plurality of address latches.

### Claim 19 (depends on 10)

The system of claim 10, further comprising:
a system interconnect, wherein the corresponding pins of the first compiled memory and the corresponding pins of the second compiled memory are coupled to the system interconnect; and
a processor coupled to the system interconnect.

### Claim 20

A system, comprising:
a plurality of compiled memories, each compiled memory including N corresponding latches coupled between a corresponding set of X address pins and a corresponding pre-decoder, the corresponding pre-decoder configured to provide pre-decoded address bits which address a selected storage location in a corresponding memory array, wherein each of N and X is an integer greater than or equal to one, and wherein:
in each compiled memory, the set of N corresponding latches includes a set of X used latches and a set of Y unused latches such that N=X+Y, Y being an integer greater than or equal to one, wherein:
each of the one or more X used latches has a data input coupled to a corresponding address pin of the corresponding set of X address pins with a one-to-one correspondence between the X latches and the X address pins, a scan input, and an output configured to provide an input to the corresponding pre-decoder, and
each of the one or more Y unused latches is configured to not provide any input to the corresponding pre-decoder, and has a data input coupled to a data input of a used latch within the set of X used latches of the compiled memory and to the corresponding address pin of the used latch, and has a scan input.