# US 12,181,521 B2 · At-speed test access port operations

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- Number: US 12,181,521 B2
- Document ID: US12181521B2
- Status: Granted
- Kind: B2
- Application number: 18/386,301
- Filed: 2023-11-02
- Published: 2024-02-22
- Granted: 2024-12-31
- Earliest claimed: 2010-07-29
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US12181521B2

## CPC

- G01R 31/318555: {Control logic}
- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318572: {Input/Output interfaces}
- G06F 11/26: Functional testing
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/122: Pixel-defining structures or layers, e.g. banks
- H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT]
- H10K 59/124: Insulating layers formed between TFT elements and OLED elements
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/1201: {Manufacture or treatment}
- H10K 2102/00: Constructional details relating to the organic devices covered by this subclass
- H10K 2102/103: {comprising indium oxides, e.g. ITO}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

## Claims

### Claim 1

A device comprising:
a test data in (TDI) terminal;
a test data out (TDO) terminal;
a test mode select (TMS) terminal;
a test clock (TCK) terminal;
test compression architecture including:
a decompressor coupled to the TDI terminal;
parallel data registers coupled to the decompressor;
a compressor coupled to the parallel data register and coupled to the TDO terminal;
a router circuit coupled to the parallel data registers; and
a command circuit coupled to the router circuit, coupled to the TMS terminal, and coupled to the TCK terminal.

### Claim 2 (depends on 1)

The device of claim 1, further comprising a test access port (TAP) state machine coupled to the router circuit, coupled to the TMS terminal, and coupled to the TCK terminal.

### Claim 3 (depends on 2)

The device of claim 2, wherein the command circuit is configured to receive a command from the TMS terminal while the TAP state machine is operating in a shift state.

### Claim 4 (depends on 3)

The device of claim 3, wherein the command circuit is configured to cause, in response to the received command, the parallel data registers to operate in a capture state while the TAP state machine is operating in the shift state.

### Claim 5 (depends on 4)

The device of claim 4, wherein the TAP state machine is configured to remain in the shift state while the command circuit causes the parallel data registers to operate in the capture state.

### Claim 6 (depends on 4)

The device of claim 4, wherein the command circuit is configured to cause the parallel data registers to operate in the capture state and an update state while the TAP state machine is operating in the shift state.

### Claim 7 (depends on 2)

The device of claim 2,
wherein the TAP state machine is configured to receive TMS inputs from the TMS terminal on a first edge of a TCK signal received from the TCK terminal,
wherein the command circuit is configured to receive command inputs from the TMS terminal on a second edge of the TCK signal, and
wherein the first edge of the TCK signal is different from the second edge of the TCK signal.

### Claim 8 (depends on 7)

The device of claim 7, wherein the TAP state machine is configured to ignore the command inputs received from the TMS terminal on the second edge of the TCK signal.

### Claim 9 (depends on 1)

The device of claim 1,
wherein the TDI terminal is a first TDI terminal,
wherein the TDO terminal is a first TDO terminal, and
wherein the device further comprises:
a second TDI terminal coupled to the decompressor; and
a second TDO terminal coupled to the compressor.

### Claim 10 (depends on 1)

The device of claim 1,
wherein the TDI terminal is a single TDI terminal,
wherein the TDO terminal is a single TDO terminal, and
wherein the device include only one TDI terminal and only one TDO terminal.

### Claim 11 (depends on 1)

The device of claim 1, wherein the parallel data registers are configured to:
receive a control signal from the router circuit; and
perform capture and shift operations in response to the control signal.

### Claim 12 (depends on 1)

The device of claim 1, wherein the decompressor is configured to:
receive a control signal from the router circuit; and
based on the control signal:
input compressed stimulus data from the TDI terminal;
decompress the compressed stimulus data; and
output the decompressed stimulus data to the parallel data registers.

### Claim 13 (depends on 1)

The device of claim 1, wherein the compressor is configured to:
receive a control signal from the router circuit; and
based on the control signal:
input response data from the parallel data registers;
compact the response data; and
output the compacted data to the TDO terminal.

### Claim 14

A device comprising:
a test data in (TDI) terminal;
a test data out (TDO) terminal;
a test mode select (TMS) terminal;
a test clock (TCK) terminal;
test compression architecture including:
a decompressor including an input coupled to the TDI terminal, wherein the decompressor further includes an output;
parallel data registers coupled to the output of the decompressor;
a compressor including an input coupled to the parallel data register, wherein the compressor further includes an output coupled to the TDO terminal;
a router circuit coupled to the parallel data registers;
a test access port (TAP) state machine coupled to the router circuit, coupled to the TMS terminal, and coupled to the TCK terminal; and
a command circuit coupled to the router circuit, coupled to the TMS terminal, and coupled to the TCK terminal.

### Claim 15 (depends on 14)

The device of claim 14, wherein the command circuit is configured to:
receive a command from the TMS terminal while the TAP state machine is operating in a shift state; and
cause, in response to the received command, the parallel data registers to operate in a capture state while the TAP state machine is operating in the shift state.

### Claim 16 (depends on 15)

The device of claim 15, wherein the TAP state machine is configured to remain in the shift state while the command circuit causes the parallel data registers to operate in the capture state.

### Claim 17 (depends on 15)

The device of claim 15, wherein the command circuit is configured to cause the parallel data registers to operate in the capture state and an update state while the TAP state machine is operating in the shift state.

### Claim 18 (depends on 14)

The device of claim 14,
wherein the TAP state machine is configured to receive TMS inputs from the TMS terminal on a first edge of a TCK signal received from the TCK terminal,
wherein the command circuit is configured to receive command inputs from the TMS terminal on a second edge of the TCK signal, and
wherein the first edge of the TCK signal is different from the second edge of the TCK signal.

### Claim 19 (depends on 18)

The device of claim 18, wherein the TAP state machine is configured to ignore the command inputs received from the TMS terminal on the second edge of the TCK signal.

### Claim 20

A device comprising:
a test data in (TDI) terminal;
a test data out (TDO) terminal;
a test mode select (TMS) terminal;
a test clock (TCK) terminal;
test compression architecture including:
a decompressor including an input coupled to the TDI terminal, wherein the decompressor further includes an output;
parallel data registers coupled to the output of the decompressor;
a compressor including an input coupled to the parallel data register, wherein the compressor further includes an output coupled to the TDO terminal;
a router circuit coupled to the parallel data registers;
a test access port (TAP) state machine coupled to the router circuit, coupled to the TMS terminal, and coupled to the TCK terminal, wherein the TAP state machine is configured to receive TMS inputs from the TMS terminal on a first edge of a TCK signal received from the TCK terminal; and
a command circuit coupled to the router circuit, coupled to the TMS terminal, and coupled to the TCK terminal,
wherein the command circuit is configured to:
receive command inputs from the TMS terminal on a second edge of the TCK signal, wherein the first edge of the TCK signal is different from the second edge of the TCK signal;
receive a command from the TMS terminal while the TAP state machine is operating in a shift state; and
cause, in response to the received command, the parallel data registers to operate in a capture state while the TAP state machine is operating in the shift state.