# US 12,181,518 B2 · Semiconductor device with interface structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,181,518 B2 - Document ID: US12181518B2 - Status: Granted - Kind: B2 - Application number: 17/509,205 - Filed: 2021-10-25 - Published: 2023-04-27 - Granted: 2024-12-31 - Earliest claimed: 2021-10-25 - Assignees: Nanya Technology Corporation - Applicants: Nanya Technology Corporation - Inventors: Chun-Huang Yu - Web page: https://patentgrep.com/patent/US12181518B2 ## CPC - G01R 31/2896: {Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00)} - G01R 31/28: Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00}) - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - G01R 31/2886: {Features relating to contacting the IC under test, e.g. probe heads; chucks (G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06)} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present application discloses a semiconductor device with an interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment. ## Claims ### Claim 1 A semiconductor device, comprising: an interface board fixed onto and electrically coupled to a chuck of a testing equipment; and a first object positioned on a first surface of the interface board and electrically coupled to the interface board; a through board via disposed in the interface board; wherein the interface board includes a lower connector positioned on a second surface of the interface board, the second surface is opposite to the first surface and is faced toward the chuck, and the chuck of the testing equipment includes a resilient connecting unit faced toward the second surface of the interface board and electrically coupled with the lower connector; wherein a board pad is disposed between the second surface of the interface board and the chuck of the testing equipment, the board pad is electrically coupled to the lower connector and the through board via and the board pad is contacted with the lower connector and the through board via, wherein a width of the board pad is greater than a width of the through board via; wherein the first object is analyzed by the testing equipment; wherein the through board via is disposed between the first surface and the second surface of the interface board and the through board via is electrically coupled with the resilient connecting unit of the chuck of the testing equipment via the board pad and the lower connector. ### Claim 2 (depends on 1) The semiconductor device of claim 1, further comprising a fixing unit positioned along the interface board and extending to the chuck to fix the interface board onto the chuck. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the fixing unit is a screw. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the lower connector and the chuck are electrically coupled through a chuck connector in which the resilient connecting unit is disposed. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the chuck connector is a pogo pin. ### Claim 6 (depends on 4) The semiconductor device of claim 4, wherein the chuck connector is a conductive polymer. ### Claim 7 (depends on 4) The semiconductor device of claim 4, wherein the interface board comprises a test pattern electrically coupled the first object and the lower connector. ### Claim 8 (depends on 7) The semiconductor device of claim 7, wherein the test pattern comprises the through board via positioned along the interface board and contacts the lower connector. ### Claim 9 (depends on 8) The semiconductor device of claim 8 wherein the first object comprises: a package substrate positioned on the first surface of the interface board and electrically connected to the interface board; a first semiconductor die positioned on the package substrate; and a wire electrically coupled the first semiconductor die and the package substrate. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the package substrate and the interface board are electrically coupled through an upper connector. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the upper connector is a solder ball. ### Claim 12 (depends on 11) The semiconductor device of claim 11, further comprising a second semiconductor die positioned on the package substrate, next to the first semiconductor die, and electrically coupled to the package substrate. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the first semiconductor die and the second semiconductor die have a same layout. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein a thickness of the interface board is greater than a thickness of the package substrate.