# US 12,181,517 B2 · Method for detecting memory chip

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- Number: US 12,181,517 B2
- Document ID: US12181517B2
- Status: Granted
- Kind: B2
- Application number: 17/446,986
- Filed: 2021-09-07
- Published: 2023-03-09
- Granted: 2024-12-31
- Earliest claimed: 2021-09-07
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Yan-De Lin; Jui-Hsiu Jao
- Web page: https://patentgrep.com/patent/US12181517B2

## CPC

- G01R 31/2893: {Handling, conveying or loading, e.g. belts, boats, vacuum fingers (G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H10P72/00)}
- G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]}
- G01R 31/2896: {Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00)}
- G01R 31/52: Testing for short-circuits, leakage current or ground faults
- G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C 2029/5002: {Characteristic}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for detecting a memory chip includes the following steps coupling a detecting circuit to a first area and a second area of the memory chip, the second area is not overlapped with the first area; inputting a first detecting signal from the detecting circuit to the first area of the memory chip; burning out a cell of the detecting circuit; and inputting a second detecting signal from the detecting circuit to the second area of the memory chip.

## Claims

### Claim 1

A method for detecting a memory chip, comprising:
coupling a detecting circuit to a first area and a second area of the memory chip, wherein the second area is not overlapped with the first area;
inputting a first detecting signal from the detecting circuit to the first area of the memory chip;
burning out a cell of the detecting circuit; and
inputting a second detecting signal from the detecting circuit to the second area of the memory chip.

### Claim 2 (depends on 1)

The method for detecting the memory chip of claim 1, wherein inputting the first detecting signal from the detecting circuit to the first area of the memory chip comprises:
determining whether the first area of the memory chip is normal or not.

### Claim 3 (depends on 2)

The method for detecting the memory chip of claim 2, wherein inputting the second detecting signal from the detecting circuit to the second area of the memory chip comprises:
determining whether the second area of the memory chip is normal or not.

### Claim 4 (depends on 1)

The method for detecting the memory chip of claim 1, further comprising:
turning on a switch of the detecting circuit to be a resistance such that the second detecting signal is transmitted to the second area of the memory chip according a control signal.

### Claim 5 (depends on 1)

The method for detecting the memory chip of claim 1, further comprising:
removing the detecting circuit from the memory chip during a manufacturing process.

### Claim 6 (depends on 1)

The method for detecting the memory chip of claim 1, wherein the memory chip comprises word lines and bit lines, wherein inputting the first detecting signal from the detecting circuit to the first area of the memory chip comprises:
inputting the first detecting signal to the word lines and inputting the first detecting signal to the bit lines independently.

### Claim 7 (depends on 1)

The method for detecting the memory chip of claim 1, wherein the memory chip comprises word lines and bit lines, wherein inputting the first detecting signal from the detecting circuit to the first area of the memory chip comprises:
inputting the first detecting signal to the word lines and inputting the first detecting signal to the bit lines simultaneously.