# US 12,181,512 B2 · Semiconductor devices comprising failure detectors for detecting failure of bipolar junction transistors and methods for detecting failure of the bipolar junction transistors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,181,512 B2 - Document ID: US12181512B2 - Status: Granted - Kind: B2 - Application number: 17/984,332 - Filed: 2022-11-10 - Published: 2023-09-21 - Granted: 2024-12-31 - Earliest claimed: 2022-03-16 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Donghun Heo; Himchan Park; Cheolhwan Lim - Web page: https://patentgrep.com/patent/US12181512B2 ## CPC - G01R 31/2608: {for testing bipolar transistors} - G01R 31/2619: {for measuring thermal properties thereof} - G01K 7/01: using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence) - G01K 15/007: {Testing} - G01R 19/10: Measuring sum, difference or ratio - H10D 84/611: {Combinations of BJTs and one or more of diodes, resistors or capacitors} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G01K: MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR (radiation pyrometry G01J5/00) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device may include a voltage generator configured to generate a first base-emitter voltage of a first bipolar junction transistor, and a failure detector configured to generate a failure signal by comparing the first base-emitter voltage with an upper limit reference voltage and a lower limit reference voltage. The failure detector may include a second bipolar junction transistor a current source configured to generate a bias current, a first resistor coupled between the current source and a emitter of the second bipolar junction transistor to generate the upper limit reference voltage, a second resistor and a third resistor configured to divide a second base-emitter voltage of the second bipolar junction transistor to generate the lower limit reference voltage, and a first and second comparator configured to compare the first base-emitter voltage with the upper limit reference voltage and the lower limit reference voltage, respectively, to generate respective failure signals. ## Claims ### Claim 1 A semiconductor device, comprising: a voltage generator configured to generate a first base-emitter voltage of a first bipolar junction transistor; and a failure detector configured to generate a failure signal by comparing the first base-emitter voltage with an upper limit reference voltage and a lower limit reference voltage; wherein the failure detector comprises: a second bipolar junction transistor in which a base terminal and a collector terminal are grounded; a current source configured to generate a bias current; a first resistor coupled between the current source and an emitter terminal of the second bipolar junction transistor to generate the upper limit reference voltage; a second resistor and a third resistor configured to divide a second base-emitter voltage of the second bipolar junction transistor to generate the lower limit reference voltage; a first comparator configured to compare the first base-emitter voltage with the upper limit reference voltage and configured to generate a first failure signal; and a second comparator configured to compare the first base-emitter voltage with the lower limit reference voltage and configured to generate a second failure signal. ### Claim 2 (depends on 1) The device of claim 1, wherein the first bipolar junction transistor and the second bipolar junction transistor have the same structure. ### Claim 3 (depends on 1) The device of claim 1, wherein a positive input terminal (+) of the first comparator is configured to receive the first base-emitter voltage, and a negative input terminal (−) of the first comparator is configured to receive the upper limit reference voltage. ### Claim 4 (depends on 3) The device of claim 3, wherein a positive input terminal (+) of the second comparator is configured to receive the lower limit reference voltage, and a negative input terminal (−) of the second comparator is configured to receive the first base-emitter voltage. ### Claim 5 (depends on 1) The device of claim 1, wherein the first and second bipolar junction transistors are PNP type bipolar junction transistors. ### Claim 6 (depends on 1) The device of claim 1, wherein a rate of change with respect to a temperature of the upper limit reference voltage or the lower limit reference voltage is the same as a rate of change with respect to the temperature of the first base-emitter voltage. ### Claim 7 (depends on 1) The device of claim 1, wherein the voltage generator is configured to generate a temperature proportional voltage or a temperature complementary voltage based on the first base-emitter voltage. ### Claim 8 (depends on 1) The device of claim 1, wherein the first bipolar junction transistor and the second bipolar junction transistor are configured to operate under the same bias condition. ### Claim 9 A semiconductor device, comprising: a first bipolar junction transistor configured to generate a first base-emitter voltage; a second bipolar junction transistor configured to generate a second base-emitter voltage; a reference generator configured to generate at least one reference voltage based on the second base-emitter voltage; and a comparator configured to compare the generated at least one reference voltage and the first base-emitter voltage and generate a failure signal based on the comparison. ### Claim 10 (depends on 9) The device of claim 9, wherein the reference generator includes: a first resistor connected between a current source and an emitter terminal of the second bipolar junction transistor to generate an upper limit reference voltage; and and a second resistor and a third resistor connected between the emitter terminal and a ground, and configured to divide the second base-emitter voltage to generate a lower limit reference voltage. ### Claim 11 (depends on 10) The device of claim 10, wherein the upper limit reference voltage has a magnitude that is a sum of the second base-emitter voltage and a first offset voltage resulting from the first resistor. ### Claim 12 (depends on 10) The device of claim 10, wherein the comparator includes: a first comparator configured to generate a first failure signal based on a comparison of the first base-emitter voltage with the upper limit reference voltage; and a second comparator configured to generate a second failure signal based on a comparison of the first base-emitter voltage with the lower limit reference voltage. ### Claim 13 (depends on 12) The device of claim 12, wherein the first base-emitter voltage is input to both a positive input terminal (+) of the first comparator and a negative input terminal (−) of the second comparator. ### Claim 14 (depends on 10) The device of claim 10, wherein a first emitter current is provided to the first bipolar junction transistor and a second emitter current is provided to the second bipolar junction transistor, the first and second emitter currents equally biased such that a rate of change with respect to temperature of each of the upper limit reference voltage and the lower limit reference voltage and a rate of change with respect to temperature of the first base-emitter voltage are the same. ### Claim 15 (depends on 14) The device of claim 14, wherein the first bipolar junction transistor and the second bipolar junction transistor have the same structure. ### Claim 16 (depends on 9) The device of claim 9, wherein a base terminal and a collector terminal of each of the first bipolar junction transistor and the second bipolar junction transistor are grounded. ### Claim 17 A method for detecting a failure in a semiconductor device using a bipolar junction transistor, comprising: generating a first base-emitter voltage from a first bipolar junction transistor; generating a second base-emitter voltage from a second bipolar junction transistor; generating an upper limit reference voltage and a lower limit reference voltage from the second base-emitter voltage; and generating, using a comparator, a failure signal based on comparing the first base-emitter voltage with the upper limit reference voltage or the lower limit reference voltage. ### Claim 18 (depends on 17) The method of claim 17, wherein a base terminal and a collector terminal of each of the first bipolar junction transistor and the second bipolar junction transistor are grounded. ### Claim 19 (depends on 17) The method of claim 17, wherein an equal magnitude of current is supplied to emitter terminals of each of the first bipolar junction transistor and the second bipolar junction transistor. ### Claim 20 (depends on 17) The method of claim 17, wherein the first bipolar junction transistor and the second bipolar junction transistor have the same structure.