# US 12,181,432 B2 · Semiconductor devices including crack sensor

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- Number: US 12,181,432 B2
- Document ID: US12181432B2
- Status: Granted
- Kind: B2
- Application number: 18/464,040
- Filed: 2023-09-08
- Published: 2023-12-28
- Granted: 2024-12-31
- Earliest claimed: 2021-10-13
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jong Su Kim
- Web page: https://patentgrep.com/patent/US12181432B2

## CPC

- G01N 27/20: Investigating the presence of flaws
- H10D 1/47: Resistors having no potential barriers
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers}
- G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a target layer disposed on a substrate, and a crack sensor for detecting a crack generated in the target layer. The crack sensor includes a first conductive pattern positioned at a bottom surface of the target layer, a second conductive pattern positioned on a top surface of the target layer, the top surface being opposite to the bottom surface of the target layer, a plurality of resistors, and nodes. The plurality of resistors are connected in parallel to each other through the first conductive pattern and the second conductive pattern. Each of the plurality of resistors is disposed to substantially penetrate the target layer.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate including chip regions and a scribe lane region;
a target layer disposed over the substrate; and
a crack sensor in the target layer,
wherein the crack sensor includes:
a first conductive pattern positioned below the target layer;
a second conductive pattern positioned over the target layer;
a plurality of resistors substantially penetrating the target layer, the plurality of resistors connected in parallel to each other through the first conductive pattern and the second conductive pattern, wherein each of the plurality of resistors is disposed sequentially away from the chip region; and
a first node and a second node connected to the first conductive pattern and the second conductive patterns, respectively.

### Claim 2

A semiconductor device comprising:
a target layer disposed over a substrate; and
a crack sensor in the target layer,
wherein the crack sensor includes:
a first conductive pattern positioned below the target layer;
a second conductive pattern positioned over the target layer;
a plurality of resistors substantially penetrating the target layer, the plurality of resistors connected in parallel to each other through the first conductive pattern and the second conductive pattern; and
a first node and a second node connected to the first conductive pattern and the second conductive pattern, respectively.

### Claim 3

A semiconductor device comprising:
a substrate including chip regions and a scribe lane region;
a target layer disposed over the substrate; and
a crack sensor in a portion of the scribe lane region,
wherein the crack sensor includes:
a first conductive pattern positioned below the target layer;
a second conductive pattern positioned over the target layer, and
a plurality of resistors substantially penetrating the target layer, the plurality of resistors connected in parallel to each other through the first conductive pattern and the second conductive pattern, and
wherein each of the plurality of resistors is disposed sequentially away from the chip region.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein each of the plurality of resistors is configured to provide substantially the same resistance values.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the plurality of resistors are configured to provide different resistance values from each other.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the plurality of resistors corresponds to a different number of conductive vias that substantially penetrate the target layer.