Error correction code circuit, memory device including error correction code circuit, and operation method of error correction code circuit

An error correction code (ECC) circuit configured to correct first data based on the first data and first parity data stored in a memory device, comprising:

• a syndrome generator configured to generate bits of a syndrome based on the first data and the first parity data from the memory device;
• a syndrome decoding circuit configured to compare the bits of the syndrome and bits of each column of a parity-check matrix to generate an error vector;
• a correction logic circuit configured to generate error-corrected data based on the error vector and the first data;
• and
• a fast decoding status flag (DSF) generator configured to generate a decoding status flag indicating a decoding status for the error-corrected data based on the bits of the syndrome and bits of a simplified-parity-check matrix,
• wherein the bits of the simplified-parity-check matrix are generated from bits of the parity-check matrix, and includes only information about a part of the bits of the parity-check matrix,
• wherein the error vector includes information about a bit position of the first data at which an error occurs,
• wherein a value of each bit of the parity-check matrix is predetermined, and
• wherein the decoding status flag indicates whether at least one of a correctable error, an uncorrectable error and a non-error is included in the first data.

An operation method of an error correction code (ECC) circuit configured to correct first data based on the first data and first parity data stored in a memory device, the method comprising:

• generating bits of a syndrome based on the first data and the first parity data;
• generating an error vector based on the bits of the syndrome and bits of a parity-check matrix;
• performing a logical operation on the error vector and the first data to generate error-corrected data;
• generating a decoding status flag based on the bits of the syndrome and bits of a simplified-parity-check matrix generated based on the bits of the parity-check matrix;
• and
• sending the error-corrected data and the decoding status flag to a memory controller,
• wherein the generating of the error vector and the generating of the decoding status flag are performed in parallel,
• wherein the error vector includes information about a bit position of the first data at which an error occurs,
• wherein a value of each bit of the parity-check matrix is predetermined, and
• wherein the decoding status flag indicates whether at least one of a correctable error, an uncorrectable error, and a non-error is included in the first data.