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US 12,176,918 B2Granted
Hybrid LDPC decoder with mixed precision components
AssigneeIntel Corporation
InventorsDebarnab Mitra, Santhosh K. Vanaparthy
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Abstract
An embodiment of an electronic apparatus may comprise one or more substrates, and a decoder coupled to the one or more substrates, the decoder including logic to perform a first decode stage with a first fixed quantization width, and perform a second decode stage with a second fixed quantization width that is different from the first fixed quantization width. Other embodiments are disclosed and claimed.
Claims17
An electronic apparatus, comprising:
- one or more substrates;
- and
- a decoder coupled to the one or more substrates, the decoder including circuitry to:
- provide a plurality of nodes of a bipartite graph, the plurality of nodes comprising variable nodes and check nodes;
- calculate a sum value, during a sum-stage, based on first messages which are communicated each from a respective one of the check nodes to a respective one of the variable nodes;
- and
- calculate a difference value, during a min-stage, based on a second message which is communicated from a respective one of the variable nodes to a respective one of the check nodes;
- wherein:
- the second message is based on the sum value;
- and
- a first fixed quantization width of the sum value is greater than a second fixed quantization width of the difference value.
8 more elements
An electronic system, comprising:
- a controller;
- memory;
- and
- a decoder communicatively coupled to the controller and the memory, the decoder including circuitry to:
- provide a plurality of nodes of a bipartite graph, the plurality of nodes comprising variable nodes and check nodes;
- calculate a sum value, during a sum-stage, based on first messages which are communicated each from a respective one of the check nodes to a respective one of the variable nodes;
- and
- calculate a difference value, during a min-stage, based on a second message which is communicated from a respective one of the variable nodes to a respective one of the check nodes;
- wherein:
- the second message is based on the sum value;
- and
- a first fixed quantization width of the sum value is greater than a second fixed quantization width of the difference value.
9 more elements
A method of decoding parity information, the method comprising:
- calculating a sum value, during a sum-stage, based on first messages which are communicated each from a respective one of check nodes of a decoder circuit to a respective one of variable nodes of the decoder circuit;
- and
- calculating a difference value, during a min-stage, based on a second message which is communicated from a respective one of the variable nodes to a respective one of the check nodes;
- wherein:
- the second message is based on the sum value;
- and
- a first fixed quantization width of the sum value is greater than a second fixed quantization width of the difference value.
4 more elements
Dependencies are inferred from the claim text.