Method and device in UE and base station for wireless communication

A method in a second node for wireless communication, wherein the second node comprises a receiver and a processor;

• the method comprising:
• the receiver receiving a first radio signal;
• the processor performing channel decoding based on polar coding to recover a first bit block from the first radio signal, comprising recovering a second bit block and a third bit block, wherein the first bit block comprises all bits in the second bit block and all bits in the third bit block;
• wherein:
• the third bit block is dependent on a Cyclic Redundancy Check (CRC) bit block of a fourth bit block;
• the fourth bit block is composed of all bits in the second bit block and all bits in a fifth bit block, all bits in the fifth bit block are 1;
• in the fourth bit block, any one bit in the fifth bit block is positioned before any one bit in the second bit block, and the fifth bit block is composed of K bits, the K being a positive integer;
• the first bit block does not include the fifth bit block;
• when a number of bits in the second bit block is equal to Q1, the K is equal to K1;
• when a number of bits in the second bit block is equal to Q2, the K is equal to K2;
• the Q1 is less than the Q2, the K1 is less than or equal to the K2;
• the Q1, the Q2, the K1 and the K2 are positive integers respectively;
• the second node is a UE, the second bit block includes downlink control information, the first radio signal is received by the second node on a PDCCH;
• a polynomial formed by the fourth bit block and the CRC bit block of the fourth bit block is divisible by the CRC cyclic generator polynomial on GF(2), that is, a remainder obtained after the polynomial formed by the fourth bit block and the CRC bit block of the fourth bit block is divided by the CRC cyclic generator polynomial is zero.

An equipment in a first node for wireless communication, comprising a processor and a transmitter, wherein:

• the processor generates a first bit block, wherein generation of the first bit block includes generating a third bit block using a Cyclic Redundancy Check (CRC) bit block of a fourth bit block, and includes composing the fourth bit block from a second bit block and a fifth bit block, all bits in the fifth bit block are 1, the first bit block comprises all bits in the second bit block and all bits in the third bit block;
• the processor performs channel coding based on polar coding using the first bit block for an input of the channel coding and using an output of the channel coding for generating a first radio signal;
• and
• the transmitter transmits the first radio signal;
• wherein:
• in the fourth bit block, any one bit in the fifth bit block is positioned before any one bit in the second bit block, and the fifth bit block is composed of K bits, the K being a positive integer;
• the input of the channel coding does not include the fifth bit block;
• when a number of bits in the second bit block is equal to Q1, the K is equal to K1;
• when a number of bits in the second bit block is equal to Q2, the K is equal to K2;
• the Q1 is less than the Q2, the K1 is less than or equal to the K2;
• the Q1, the Q2, the K1 and the K2 are positive integers respectively;
• the first node is a base station, the second bit block includes downlink control information, the first radio signal is transmitted on a PDCCH;
• a polynomial formed by the fourth bit block and the CRC bit block of the fourth bit block is divisible by the CRC cyclic generator polynomial on GF(2), that is, a remainder obtained after the polynomial formed by the fourth bit block and the CRC bit block of the fourth bit block is divided by the CRC cyclic generator polynomial is zero.

An equipment in a second node for wireless communication, comprising a receiver and a processor, wherein:

• the receiver receives a first radio signal;
• and
• the processor performs channel decoding based on polar coding to recover a first bit block from the first radio signal, wherein recovering of the first bit block includes recovering a second bit block and a third bit block, the first bit block comprises all bits in the second bit block and all bits in the third bit block;
• wherein:
• the third bit block is dependent on a Cyclic Redundancy Check (CRC) bit block of a fourth bit block;
• the fourth bit block is composed of all bits in the second bit block and all bits in a fifth bit block, all bits in the fifth bit block are 1;
• in the fourth bit block, any one bit in the fifth bit block is positioned before any one bit in the second bit block, and the fifth bit block is composed of K bits, the K being a positive integer;
• the first bit block does not include the fifth bit block;
• when a number of bits in the second bit block is equal to Q1, the K is equal to K1;
• when a number of bits in the second bit block is equal to Q2, the K is equal to K2;
• the Q1 is less than the Q2, the K1 is less than or equal to the K2;
• the Q1, the Q2, the K1 and the K2 are positive integers respectively;
• the second node is a UE, the second bit block includes downlink control information, the first radio signal is transmitted on a PDCCH;
• a polynomial formed by the fourth bit block and the CRC bit block of the fourth bit block is divisible by the CRC cyclic generator polynomial on GF(2), that is, a remainder obtained after the polynomial formed by the fourth bit block and the CRC bit block of the fourth bit block is divided by the CRC cyclic generator polynomial is zero.