Linear multi-level DAC

A digital-to-analog converter (DAC) comprising:

• a set of capacitors;
• a charge accumulator coupled to the set of capacitors;
• and
• a controller coupled to the set of capacitors, the controller configured to:
• map an input code to a non-uniformly distributed input code, the non-uniformly distributed input code comprising a first input code portion and a second input code portion,
• cause a first charge to be transferred from the set of capacitors to the charge accumulator based on the first input code portion, and
• cause a second charge to be transferred from the set of capacitors to the charge accumulator based on the second input code portion by selectively applying pairs of a plurality of reference voltage pairs across respective subsets of the set of capacitors, wherein, for non-zero second input code portions, each pair of the plurality of pairs of reference voltages share one common reference voltage with an adjacent pair of the plurality of pairs of reference voltages, each of the respective subsets of the set of capacitors is different from one another, and each of the plurality of pairs of reference voltages is different from one another.

A sigma-delta analog-to-digital converter (ADC) comprising:

• an integrator;
• a quantizer coupled to an output of the integrator;
• a plurality of capacitors coupled to an input of the integrator;
• a reference voltage generator comprising outputs configured to provide a plurality of reference voltages;
• a switching network coupled between the reference voltage generator and the plurality of capacitors;
• and
• a controller configured to:
• map an input code to a non-uniformly distributed input code comprising a first input code portion representing one or more most significant bits, and a second input code portion representing one or more least significant bits,
• successively couple the outputs of the reference voltage generator to each of the plurality of capacitors via the switching network according to a respective value of the non-uniformly distributed input codes to apply a voltage difference, wherein each of the plurality of capacitors is used for each value of the non-uniformly distributed input code, and
• for a non-zero second input code portion of the non-uniformly distributed input code, apply a first voltage difference formed by a first pair of outputs of the reference voltage generator to a first subset of the plurality of capacitors, and apply a second voltage difference formed by a second pair of outputs of the reference voltage generator to a second subset of the plurality of capacitors different from the first subset, wherein the first pair of outputs share a common output with the with second pair of outputs.