Back to results
US 12,176,904 B2Granted
Alarm systems and circuits
AssigneeArm Limited
InventorsShashank Guruprasad, Roma Rudra, Mikael Yves Marie Rien, Karthik Sankaranarayanan
Life of this patent
Estimating the term…
Abstract
According to one implementation of the present disclosure, a circuit includes: two or more metal wires, respective XOR gates coupled to each of the two or more top metal wires, a shift register having outputs coupled to the XOR gates, an OR gate configured to receive each of the outputs of the XOR gates, and a latch configured to receive an output of the OR gate and transmit an output signal corresponding to an alarm signal.
Claims19
A circuit comprising:
- two or more metal wires;
- respective XOR gates, wherein:
- each XOR gate is configured to compare a digital bit at a first portion of a respective wire of the two or more metal wires to a digital bit at a second portion of the respective wire;
- respective AND gates having outputs coupled directly to the respective XOR gates by way of the two or more metal wires;
- a linear feedback shift register (LFSR) having outputs coupled to inputs of the respective AND gates;
- and
- a latch configured to receive a combined signal of the XOR gates and transmit an output signal corresponding to an alarm signal.
4 more elements
A system comprising:
- a shift register and comparator block configured to receive an enable or disable signal, two or more seed bit values, a clock signal, and output an alarm signal, wherein:
- the shift register and comparator block comprises XOR gates with respective first and second inputs coupled to respective first and second portions of a respective wire of two or more metal shield wires,
- the shift register and comparator block outputs the alarm signal by way of outputs of the XOR gates,
- the shift register and comparator block comprises a linear feedback shift register (LFSR) with outputs coupled to the XOR gates by way of AND gates and the two or more metal wires, and
- the AND gates have outputs coupled directly to the XOR gates by way of the two or more metal wires.
2 more elements
A method comprising:
- providing a one-time programmable (OTP) per-chip value;
- providing a boot counter;
- generating a unique seed value based on a combination of the per-chip value and the boot counter;
- coupling outputs of a linear feedback shift register (LFSR) to XOR gates by way of AND gates and multiple respective metal shield wires, wherein each of the AND gates comprises an output coupled directly to first and second inputs of each of the XOR gates by way of the multiple respective metal shield wires;
- applying the unique seed value to the shift register so as to drive respective signals to the XOR gates by way of the multiple respective metal shield wires;
- and
- generating an alarm signal via outputs of the XOR gates based on the respective signals to the XOR gates.
4 more elements
Dependencies are inferred from the claim text.