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US 12,176,064 B2Granted
Apparatus and methods employing asynchronous FIFO buffer with read prediction
AssigneeAdvanced Micro Devices, Inc.
InventorsRichard Martin Born, David M. Dahle
Life of this patent
Estimating the term…
Abstract
Methods and apparatus employ an asynchronous first-in-first-out buffer (FIFO), that includes a plurality of entries. Control logic determines a timing separation between a write header valid signal and corresponding write data valid signal for a write operation to an entry in the first-in-first-out buffer (FIFO) and performs a read of the corresponding data from the entry in the FIFO in the second clock domain, based on the determined timing separation of the write header valid signal and corresponding write data valid signal, and based on a clock frequency ratio between the first and second clock domains.
Claims20
A processor comprising:
- a first-in-first-out buffer (FIFO) comprising a plurality of entries and operative to process writes at a first clock frequency of a first clock domain and process reads at a second clock frequency of a second clock domain, the second clock domain asynchronous with the first clock domain;
- control logic configured to:
- in response to a change in frequency of either of the first clock frequency or the second clock frequency, calculate a timing separation between a write header valid signal and corresponding write data valid signal for a write operation to an entry in the FIFO;
- and
- perform a read of the corresponding data from the entry in the FIFO in the second clock domain, based on the timing separation of the write header valid signal and corresponding write data valid signal, and based on a clock frequency ratio between the first and second clock domains.
2 more elements
A method carried out by at least one processor, comprising:
- in response to a change in frequency of either of a first clock frequency or a second clock frequency in different clock domains, calculating a timing separation between a write header valid signal and corresponding write data valid signal for a write operation to an entry in a first-in-first-out buffer (FIFO) comprising a plurality of entries operative to process writes at the first clock frequency of a first clock domain and process reads at the second clock frequency of a second clock domain, the second clock domain asynchronous with the first clock domain;
- and
- performing a read of the corresponding data from the entry in the FIFO in the second clock domain, based on the timing separation of the write header and corresponding write data and based on a clock frequency ratio between the first and second clock domains.
A system comprising:
- at least one processor comprising:
- an asynchronous first-in-first-out buffer (FIFO) having a plurality of entries;
- a first clock domain operative at a first clock frequency and comprising:
- at least one write header queue configured to store a write header;
- at least one write data queue configured to store write data corresponding to the write header;
- write control logic configured to, in response to a change in frequency of either of the first clock frequency or a second and different clock frequency, calculate a timing separation between a write header valid signal and corresponding write data valid signal for a write operation to an entry in the FIFO;
- a second clock domain operative at the second and different clock frequency, and comprising:
- read header logic configured to provide a read header;
- read data logic configured to provide read data corresponding to the read header;
- a read transaction pipeline;
- and
- control logic configured to perform a read of the corresponding data from the entry in the FIFO in the second clock domain, based on the timing separation of the write header and corresponding write data, and based on a clock frequency ratio of the first clock frequency and the second clock frequency.
9 more elements
An asynchronous first-in-first-out buffer (FIFO) comprising:
- a plurality of entries and operative to process writes at a first clock frequency of a first clock domain and process reads at a second clock frequency of a second clock domain, the second clock domain asynchronous with the first clock domain;
- control logic configured to:
- in response to a change in frequency of either of the first clock frequency or the second clock frequency, calculate a timing separation between a write header valid signal and corresponding write data valid signal for a write operation to an entry in the first-in-first-out buffer;
- and
- perform a read of the corresponding data from the entry in the FIFO in the second clock domain, based on the timing separation of the write header and corresponding write data, and based on a clock frequency ratio between the first and second clock domains.
2 more elements
Dependencies are inferred from the claim text.