Signal processing method and signal processor
AssigneeRealtek Semiconductor Corp.
InventorsHong-Ru Chou, Wen-Chih Fang, Yung-Le Chang, Bo-Cheng Lin
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Abstract
A signal processing method includes the following operations: receiving an input signal and analyzing the input signal to generate a plurality of bit codes by a signal receiving circuit; temporarily storing a first part of the plurality of bit codes according to a time sequence by a shift register and starting a decoder when the shift register is full; and performing a boundary calibration according to the first part of the plurality of bit codes by the decoder when the first part of the plurality of bit codes meets a decoding table rule and a boundary detection rule.
Claims20
A signal processing method, comprising:
- receiving an input signal and analyzing the input signal to generate a plurality of bit codes by a signal receiving circuit;
- temporarily storing a first part of the plurality of bit codes according to a time sequence by a shift register, and starting a decoder when the shift register is full;
- and
- performing a boundary calibration according to the first part of the plurality of bit codes by the decoder when the first part of the plurality of bit codes meets a decoding table rule and a boundary detection rule;
- wherein the boundary detection rule comprises:
- when the first part of the plurality of bit codes corresponds to a plurality of symbolic names H in consecutive, a plurality of symbolic names N in consecutive, or a plurality of symbolic names T in consecutive, locking a decoding boundary by the decoder according to the first part of the plurality of bit codes.
A signal processor, comprising:
- a signal receiving circuit, configured to receive an input signal and to analyze the input signal to generate a plurality of bit codes;
- a shift register, configured to temporarily store a first part of the plurality of bit codes according to a time sequence;
- and
- a decoder, configured to start when the shift register is full, and configured to perform a boundary calibration according to the first part of the plurality of bit codes when the first part of the plurality of bit codes meets a decoding table rule and a boundary detection rule;
- wherein the boundary detection rule comprises:
- when the first part of the plurality of bit codes corresponds to a plurality of symbolic names H in consecutive, a plurality of symbolic names N in consecutive, or a plurality of symbolic names T in consecutive, locking a decoding boundary by the decoder according to the first part of the plurality of bit codes.
Dependencies are inferred from the claim text.