Bit error rate estimation and classification in NAND flash memory

A solid-state drive (SSD) comprising:

• a non-volatile semiconductor memory device comprising a plurality of memory cells for storing data, the memory cells arranged in memory blocks comprising rows;
• and
• a controller in communication with the plurality of memory cells, the controller configured to:
• retrieve data from a target row of memory cells of the plurality of memory cells associated with a read request received from a host using initial threshold voltages;
• decode the data using a first hard decision decoding stage;
• estimate a bit error rate (BER) of the target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails;
• classify the BER of the target row based on a first BER threshold (BER-TH1);
• and
• execute a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and execute a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.