Coprocessors with bypass optimization, variable grid architecture, and fused vector operations

A method comprising:

• issuing a given instruction operation corresponding to a given coprocessor instruction a plurality of times in a plurality of processing element circuits in a coprocessor, wherein the plurality of processing element circuits are is arranged in a first grid of one or more rows and one or more columns, wherein:
• the given coprocessor instruction is defined to cause evaluation of a second plurality of processing element circuits arranged in a second grid of one or more rows and one or more columns, wherein the second grid includes more processing element circuits than the first grid;
• the plurality of processing element circuits performs a different portion of the given instruction operation in each of the plurality of times that the given instruction operation is issued;
• and
• a number of times in the plurality of times is based on a comparison of a first number of processing element circuits in the plurality of processing element circuits and a second number, as defined by the given coprocessor instruction, of processing element circuits in the second plurality of processing element circuits.

A system comprising:

• a processor configured to process instructions defined by an instruction set;
• and
• a coprocessor coupled to the processor, wherein:
• a subset of the instructions defined by the instruction set are coprocessor instructions executable by the coprocessor;
• the processor is configured to detect a given coprocessor instruction and issue the given coprocessor instruction to the coprocessor for execution;
• and
• the coprocessor comprises:
• a plurality of processing element circuits arranged in a first grid of one or more rows and one or more columns, wherein the given coprocessor instruction is defined in the instruction set to cause evaluation of a second plurality of processing element circuits arranged in a second grid of one or more rows and one or more columns, wherein the second grid includes more processing element circuits than the first grid;
• a decode circuit configured to decode coprocessor instructions issued from the processor to the coprocessor into instruction operations;
• and
• a queue circuit coupled to the plurality of processing element circuits and to the decode circuit, wherein the queue circuit includes a scheduler circuit configured to issue instruction operations to the plurality of processing element circuits, wherein the scheduler circuit is configured to issue a given instruction operation corresponding to the given coprocessor instruction a plurality of times to complete the given coprocessor instruction, wherein the plurality of processing element circuits perform a different portion of the given instruction operation in each of the plurality of times that the instruction operation is issued.