Method for checking DFT circuit, test platform, storage medium and test system
AssigneeChangxin Memory Technologies, Inc.
InventorsTeng Shi, Kang Zhao
Life of this patent
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Abstract
A method for checking a Design for Test (DFT) circuit includes: transmitting a control signal to the DFT circuit to determine test mode signals output by the DFT circuit, with the DFT circuit being configured to sequentially select multiple address latches according to the control signal to output the test mode signals; analyzing the test mode signals to determine whether the multiple address latches in the DFT circuit have an error; and outputting a simulation result report.
Claims16
A method for checking a Design for Test (DFT) circuit, applied to a test platform, wherein the DFT circuit comprises multiple address latches, and the test platform is connected to the DFT circuit, and the method comprises:
- transmitting a control signal to the DFT circuit to determine test mode signals output by the DFT circuit, wherein the DFT circuit is configured to sequentially select multiple address latches according to the control signal to output the test mode signals;
- analyzing the test mode signals to determine whether the multiple address latches in the DFT circuit have an error;
- and
- outputting a simulation result report.
A test platform connected to a Design for Test (DFT) circuit comprising multiple address latches, comprising a test circuit, an analysis circuit, and an output circuit, wherein:
- the test circuit is configured to transmit a control signal to the DFT circuit to determine test mode signals output by the DFT circuit, wherein the DFT circuit is configured to sequentially select multiple address latches according to the control signal to output the test mode signals;
- the analysis circuit is configured to analyze the test mode signals to determine whether the multiple address latches in the DFT circuit have an error;
- and
- the output circuit is configured to output a simulation result report.
A test platform connected to a Design for Test (DFT) circuit comprising multiple address latches, the test platform comprising a memory and a processor, wherein:
- the memory is configured to store computer-executable instructions which can be run by the processor;
- and
- the processor is configured to, when the computer-executable instructions are run, perform operations of:
- transmitting a control signal to the DFT circuit to determine test mode signals output by the DFT circuit, wherein the DFT circuit is configured to sequentially select multiple address latches according to the control signal to output the test mode signals;
- analyzing the test mode signals to determine whether the multiple address latches in the DFT circuit have an error, and
- outputting a simulation result report.
Dependencies are inferred from the claim text.