Microelectronic devices, and related memory devices and electronic systems

A memory device, comprising:

• a base structure comprising a region comprising complementary metal-oxide-semiconductor (CMOS) circuitry, and an additional region horizontally neighboring the region and substantially free of the CMOS circuitry;
• a conductive routing tier overlying the base structure;
• a stack structure overlying the conductive routing tier and comprising conductive material and insulative material vertically alternating with the conductive material;
• a memory array comprising strings of memory cells extending through the stack structure, the memory array within a horizontal area of the region of the base structure;
• an additional conductive routing tier overlying the stack structure;
• conductive contacts horizontally offset from the memory array and extending between the conductive routing tier and the additional conductive routing tier;
• first conductive pads overlying the additional conductive routing tier and within a horizontal area of the additional region of the base structure, the first conductive pads in electrical communication with some of the conductive contacts;
• and
• second conductive pads overlying the additional conductive routing tier and horizontally interposed between the first conductive pads and at least some of the strings of memory cells of the memory array, the second conductive pads in electrical communication with some other of the conductive contacts.

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably connected to the input device and the output device;
• and
• a memory device operably connected to the processor device and comprising:
• a stack structure comprising conductive structures vertically interleaved with insulative structures;
• a base structure vertically underlying the stack structure and comprising a logic region including logic circuitry;
• a memory array comprising strings of memory cells vertically extending through the stack structure, the memory array positioned within a horizontal area of the logic region of the base structure;
• and
• bond pads vertically overlying the stack structure and in electrical communication with the logic circuitry, the bond pads comprising:
• first bond pads positioned outside of the horizontal area of the logic region of the base structure;
• and
• second bond pads positioned within of the horizontal area of the logic region of the base structure.