Semiconductor apparatus with inspection terminals

A semiconductor apparatus comprising:

• a memory controller;
• a CPU;
• a high-speed communication controller;
• a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller;
• a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller;
• a plurality of inspection terminals for acquiring information from the CPU and performing debugging;
• and
• a terminal mounting surface at which a plurality of coupling terminals including the plurality of memory operation terminals, the plurality of high-speed communication terminals, and the plurality of inspection terminals are distant from each other in first and second directions of the terminal mounting surface that perpendicularly intersect with each other and the plurality of inspection terminals are arranged to receive JTAG (Joint Test Action Group) standard signals, wherein
• the terminal mounting surface includes a first side, a second side located facing the first side, a third side intersecting both the first side and the second side, and a fourth side located facing the third side,
• the plurality of coupling terminals includes a first terminal row located adjacent to the third side and arranged from the first side toward the second side to extend along the first direction of the terminal mounting surface, and a second terminal row located adjacent to the fourth side and arranged from the first side toward the second side,
• the first terminal row includes a first inspection terminal among the plurality of inspection terminals,
• the second terminal row includes a second inspection terminal among the plurality of inspection terminals, and
• the first inspection terminal is arranged relative to at least one of the plurality of high-speed communication terminals in the second direction of the terminal mounting surface, and is arranged relative to at least one of the plurality of memory operation terminals in the first direction of the terminal mounting surface.

A semiconductor apparatus comprising:

• a memory controller;
• a CPU;
• a high-speed communication controller;
• a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller;
• a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller;
• a plurality of inspection terminals for acquiring information from the CPU and performing debugging;
• and
• a terminal mounting surface at which a plurality of coupling terminals including the plurality of memory operation terminals, the plurality of high-speed communication terminals, and the plurality of inspection terminals are distant from each other in first and second directions of the terminal mounting surface that intersect with each other and the plurality of inspection terminals are arranged to receive JTAG (Joint Test Action Group) standard signals, wherein
• the terminal mounting surface includes a first side, a second side located facing the first side, a third side intersecting both the first side and the second side, and a fourth side located facing the third side,
• the plurality of coupling terminals includes a first terminal row located adjacent to the third side and arranged from the first side toward the second side, and a second terminal row located adjacent to the fourth side and arranged from the first side toward the second side,
• the first terminal row includes a first inspection terminal among the plurality of inspection terminals,
• the second terminal row includes a second inspection terminal among the plurality of inspection terminals, and
• at least one of the plurality of high-speed communication terminals is disposed between the first inspection terminal and the second inspection terminal in a direction directing from the third side to the fourth side.

A semiconductor apparatus comprising:

• a memory controller;
• a CPU;
• a high-speed communication controller;
• a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller;
• a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller;
• a plurality of inspection terminals for acquiring information from the CPU and performing debugging;
• and
• a terminal mounting surface at which a plurality of coupling terminals including the plurality of memory operation terminals, the plurality of high-speed communication terminals, and the plurality of inspection terminals are distant from each other in first and second directions of the terminal mounting surface that intersect with each other and the plurality of inspection terminals are arranged to receive JTAG (Joint Test Action Group) standard signals, wherein
• the terminal mounting surface includes a first side, a second side located facing the first side, a third side intersecting both the first side and the second side, and a fourth side located facing the third side,
• the plurality of coupling terminals includes a first terminal row located adjacent to the third side and arranged from the first side toward the second side, and a second terminal row located adjacent to the fourth side and arranged from the first side toward the second side,
• the first terminal row includes a first inspection terminal among the plurality of inspection terminals,
• the second terminal row includes a second inspection terminal and a third inspection terminal among the plurality of inspection terminals,
• the third inspection terminal is located closest to the second side in the second terminal row, and
• at least one of the plurality of high-speed communication terminals is disposed between the second inspection terminal and the third inspection terminal in a direction directing from the first side to the second side.

A semiconductor apparatus comprising:

• a memory controller;
• a CPU;
• a high-speed communication controller;
• a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller;
• a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller;
• a plurality of inspection terminals for acquiring information from the CPU and performing debugging;
• and
• a terminal mounting surface at which a plurality of coupling terminals including the plurality of memory operation terminals, the plurality of high-speed communication terminals, and the plurality of inspection terminals are distant from each other in first and second directions of the terminal mounting surface that intersect with each other and the plurality of inspection terminals are arranged to receive JTAG (Joint Test Action Group) standard signals, wherein
• the terminal mounting surface includes a first side, a second side located facing the first side, a third side intersecting both the first side and the second side, and a fourth side located facing the third side,
• the plurality of coupling terminals includes a first terminal row located adjacent to the third side and arranged from the first side toward the second side, and a second terminal row located adjacent to the fourth side and arranged from the first side toward the second side,
• the first terminal row includes a first inspection terminal among the plurality of inspection terminals,
• the second terminal row includes a second inspection terminal and a third inspection terminal among the plurality of inspection terminals,
• the third inspection terminal is located closest to the second side in the second terminal row, and
• at least one of the plurality of high-speed communication terminals and at least one of the plurality of memory operation terminals are disposed between the second inspection terminal and the third inspection terminal in a direction directing from the first side to the second side.