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US 12,170,509 B2Granted
Sampling and holding electrical signals with rail-to-rail equivalent output swing
AssigneeCisco Technology, Inc.
InventorOleksiy Zabroda
Life of this patent
Estimating the term…
Abstract
A sample and hold circuit providing rail-to rail equivalent output is described. The circuit includes a sample and hold amplifier containing two separate sets of sampling capacitors, one set is coupled to a PMOS transistor differential stage and the other set is coupled to an NMOS transistor differential stage. The differential stages drive a current mirror based push-pull output differential stage to provide an output signal with ranges equivalent to a rail-to rail output signal swing.
Claims19
A circuit for sampling and holding electrical signals comprising:
- a sample and hold amplifier comprising:
- a first input node;
- a first output node;
- at least two capacitors, where each capacitor of the at least two capacitors comprises a bottom plate and a top plate, where each respective top plate is coupled to the first input node and the first output node;
- a first PMOS transistor comprising:
- a gate node connected to a bottom plate of a first capacitor of the at least two capacitors;
- and
- a drain node coupled to an input node of a first current mirror, where an output of the first current mirror is coupled to a second output node of the sample and hold amplifier;
- and
- a first NMOS transistor comprising:
- a gate node connected to a bottom plate of a second capacitor of the at least two capacitors;
- and
- a drain node coupled to an input node of a second current mirror, where an output of the second current mirror is coupled to the second output node of the sample and hold amplifier.
10 more elements
A method for sampling and holding an electrical signal:
- at first time enabling a tracking mode in a sample and hold amplifier by:
- shunting together gate nodes of an NMOS transistor differential stage and shunting together gate nodes of a PMOS transistor differential stage using a first set of switches;
- coupling together top plates from a set of sampling capacitors to at least one input node of the sample and hold amplifier, where bottom plates of the set of sampling capacitors are connected to different gate nodes of the NMOS and PMOS transistor differential stages;
- disabling a first set of PMOS current mirrors driven by the NMOS transistor differential stage;
- and
- disabling a first set of NMOS current mirrors driven by the PMOS transistor differential stage;
- and
- at second time enabling a holding mode in the sample and hold amplifier by:
- opening the first set of switches and second set of switches,
- disconnecting the set of sampling capacitors from the at least one input node;
- enabling the first set of PMOS current mirrors;
- enabling the first set of NMOS current mirrors;
- coupling a first subset of the first set of sampling capacitors to at least one output of the sample and hold amplifier to provide a holding output signal;
- and
- coupling a second subset of the sampling capacitors to at least one voltage source.
12 more elements
A circuit for sampling and holding electrical signals comprising:
- a sample and hold amplifier;
- a PMOS transistor differential stage;
- and
- an NMOS transistor differential stage, the circuit configured to perform a method comprising:
- at first time enabling a tracking mode in the sample and hold amplifier by:
- shunting together gate nodes of the NMOS transistor differential stage and shunting together gate nodes of the PMOS transistor differential stage using a first set of switches;
- coupling together top plates from a set of sampling capacitors to at least one input node of the sample and hold amplifier, where bottom plates of the set of sampling capacitors are connected to different gate nodes of the NMOS and PMOS transistor differential stages;
- disabling a first set of PMOS transistor current mirrors driven by the NMOS transistor differential stage;
- and
- disabling a first set of NMOS transistor current mirrors driven by the PMOS transistor differential stage;
- and
- at second time enabling a holding mode in the sample and hold amplifier by:
- opening the first set of switches,
- disconnecting the set of sampling capacitors from the at least one input node;
- enabling the first set of PMOS transistor current mirrors;
- enabling the first set of NMOS transistor current mirrors;
- coupling a first subset of the first set of sampling capacitors to at least one output of the sample and hold amplifier to provide a holding output signal;
- and
- coupling a second subset of the sampling capacitors to at least one voltage source.
16 more elements
Dependencies are inferred from the claim text.