Three dimensional vertically structured electronic devices
AssigneeLawrence Livermore National Security, LLC
InventorsAdam Conway, Sara Elizabeth Harrison, Rebecca Nikolic, Qinghui Shao, Lars Voss
Life of this patent
Estimating the term…
Abstract
An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.
Claims18
An apparatus, comprising:
- at least one vertical transistor, comprising:
- a substrate comprising a first semiconductor material;
- an array of three dimensional (3D) structures above the substrate, wherein each 3D structure comprises the first semiconductor material;
- a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, wherein the sidewall heterojunction layer comprises a second semiconductor material, wherein the first and second semiconductor materials have different bandgaps;
- and
- an isolation region positioned between the 3D structures.
Dependencies are inferred from the claim text.