Method of manufacturing a semiconductor device and a semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng-Wei Chang, Shahaji B. More, Yi-Ying Liu, Yueh-Ching Pai
Life of this patent
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Abstract
In method of manufacturing a semiconductor device, a source/drain epitaxial layer is formed, one or more dielectric layers are formed over the source/drain epitaxial layer, an opening is formed in the one or more dielectric layers to expose the source/drain epitaxial layer, a first silicide layer is formed on the exposed source/drain epitaxial layer, a second silicide layer different from the first silicide layer is formed on the first silicide layer, and a source/drain contact is formed over the second silicide layer.
Claims20
A semiconductor device comprising:
- a plurality of semiconductor bodies disposed and vertically arranged over a substrate, each of the plurality of semiconductor bodies including a channel region;
- a gate dielectric layer disposed on and wrapping around the channel region of each of the plurality of semiconductor bodies;
- a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region;
- a source/drain region including a source/drain epitaxial layer;
- and
- a source/drain contact disposed over and in electrical contact with the source/drain epitaxial layer, wherein:
- a first silicide layer is disposed on the source/drain epitaxial layer, and
- a second silicide layer different from the first silicide layer is disposed on the first silicide layer.
A semiconductor device comprising:
- a fin structure protruding from a semiconductor substrate and including a channel region and a source/drain region having a recess;
- a gate structure disposed over the channel region, the gate structure including a gate dielectric layer, a gate electrode layer, a sidewall spacer layer, a cap insulating layer disposed on the gate electrode layer and the sidewall spacer layer;
- a source/drain epitaxial layer disposed on the recess of the source/drain region;
- a source/drain contact disposed over and in electrical contact with the source/drain epitaxial layer;
- and
- a dielectric cover layer disposed between the source/drain contact and the cap insulating layer, wherein:
- a first silicide layer is disposed on the source/drain epitaxial layer, and
- a second silicide layer different from the first silicide layer is disposed on the first silicide layer.
A semiconductor device comprising an n-type FET and p-type FET, wherein:
- each of the n-type FET and p-type FET includes:
- a fin structure protruding from a semiconductor substrate and including a channel region and a source/drain region having a recess;
- a gate structure disposed over the channel region, the gate structure including a gate dielectric layer, a gate electrode layer, a sidewall spacer layer, a cap insulating layer disposed on the gate electrode layer and the sidewall spacer layer;
- a source/drain epitaxial layer disposed on the recess of the source/drain region;
- a source/drain contact disposed over and in electrical contact with the source/drain epitaxial layer;
- and
- a dielectric cover layer disposed between the source/drain contact and the cap insulating layer, wherein:
- an interfacial silicide layer is disposed on the source/drain epitaxial layer,
- a first silicide layer is disposed on the interfacial silicide layer,
- a second silicide layer different from the first silicide layer is disposed on the first silicide layer, and
- a thickness of the interfacial silicide layer of the n-type FET is greater than a thickness of the interfacial silicide layer of the p-type FET.
Dependencies are inferred from the claim text.