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US 12,170,125 B2Granted
Memory device and electronic device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChien-Yu Huang, Chia-En Huang, Cheng Hung Lee, Hua-Tai Shieh
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Abstract
Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.
Claims20
A method, comprising:
- providing a first column of memory cells, wherein a first local redundancy decoder circuit is operably connected to the first column of memory cells;
- providing a second column of memory cells immediately adjacent the first column of memory cells, wherein a second local redundancy decoder circuit is operably connected to the second column of memory cells and to the first column of memory cells, and wherein the first local redundancy decoder circuit differs from the second local redundancy decoder circuit and includes two inverters operable connected in series;
- providing a first pre-decoder circuit operably connected to the first local redundancy decoder circuit.
A device, comprising:
- a memory array comprising a plurality of memory cells arranged in rows and columns;
- a first local redundancy decoder circuit operably connected to a first column in the memory array;
- a second column in the memory array adjacent the first column;
- and
- a decoder controller including a first pre-decoder circuit operably connected to the first local redundancy decoder circuit, the first pre-decoder circuit including a first inverter that outputs a first input signal to the first local redundancy decoder circuit and a converter circuit that produces one or more output signals used as inputs to the first local redundancy decoder circuit.
2 more elements
A system, comprising:
- a first column of memory cells;
- a first local redundancy decoder circuit connected to the first column of memory cells;
- a second local redundancy decoder circuit that differs from the first local redundancy decoder circuit, the second local redundancy controller connected to the first local redundancy decoder circuit and to a second column of memory cells immediately adjacent the first column of memory cells;
- a first a first pre-decoder circuit connected to the first local redundancy decoder circuit, the first pre-decoder circuit including a first inverter that outputs a first input signal to the first local redundancy decoder circuit and a converter circuit that produces one or more output signals used as inputs to the first local redundancy decoder.
1 more element
Dependencies are inferred from the claim text.