Back to results
US 12,170,105 B2Granted
One time programmable (OTP) magnetoresistive random-access memory (MRAM)
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Hao Lee, Chia-Fu Lee, Yi-Chun Shih
Life of this patent
Estimating the term…
Abstract
A memory device includes a plurality of magnetoresistive random-access memory (MRAM) cells including a first one-time programmable (OTP) MRAM cell. A first OTP select transistor is connected to the first OTP MRAM cell. The first OTP select transistor configured to selectively apply a breakdown current to the first OTP MRAM cell to write the first OTP MRAM cell to a breakdown state.
Claims20
A memory device, comprising:
- a first MRAM cell array;
- a memory cell select transistor having a first threshold configured to selectively apply a first write current to a selected one of a plurality of first MRAM bit cells in the first MRAM cell array to selectively write the selected one of the first MRAM bit cells to a parallel state or an anti-parallel state;
- a first OTP select transistor having a second threshold lower than the first threshold configured to selectively apply a breakdown current higher than the first write current to a first OTP MRAM cell in the first MRAM cell array to write the first OTP MRAM cell to a breakdown state;
- a second MRAM cell array;
- a second OTP MRAM cell in the second array;
- a second OTP select transistor connected to the second OTP MRAM cell, the second OTP select transistor configured to selectively apply a breakdown current to the second OTP MRAM cell, the second OTP select transistor configured to selectively apply the breakdown current to the second OTP MRAM cell to write the second OTP MRAM cell to a breakdown state;
- and
- a memory controller configured to apply control signals to one of the first or second OTP select transistors, such that the first OTP MRAM cell is written to the breakdown state and the second OTP MRAM cell is not written to the breakdown state.
5 more elements
A method, comprising:
- controlling a memory cell select transistor to selectively apply a first write current to a selected one of a plurality of first MRAM bit cells to selectively write the selected one of the first MRAM bit cells to a parallel state or an anti-parallel state;
- determining whether a first one-time-programmable (OTP) MRAM cell has previously been written to a breakdown state;
- based on the determining, controlling an OTP select transistor to selectively apply a breakdown current higher than the first write current to the first OTP MRAM cell to write the first OTP MRAM cell to a breakdown state;
- and
- wherein the plurality of first MRAM bit cells include at least one dummy MRAM cell not connected to a corresponding one of the memory cell select transistors.
2 more elements
A method, comprising:
- providing a plurality of first MRAM bit cells;
- controlling a memory cell select transistor to selectively apply a first write current to a selected one of the plurality of first MRAM bit cells to selectively write the selected one of the first MRAM bit cells to a parallel state or an anti-parallel state;
- providing an OTP MRAM cell;
- providing a plurality of OTP select transistors coupled in parallel between the OTP MRAM cell and a first source line;
- determining a number of the OTP select transistors for applying a desired breakdown current higher than the first write current to the OTP MRAM cell;
- and
- controlling the determined number of the OTP select transistors to selectively apply the desired breakdown current to the OTP MRAM cell to write the first OTP MRAM cell to a breakdown state;
- wherein the plurality of first MRAM bit cells are arranged in a first memory array;
- and
- wherein the first memory array includes a plurality of dummy cells not connected to any of the memory cell select transistors.
7 more elements
Dependencies are inferred from the claim text.