MUX and DEMUX circuits with improved bandwidth

A circuit comprising:

• a N:1 multiplexer (MUX);
• and
• N digital-to-analog converters (DACs), each having an output that is input to the MUX,
• wherein:
• the MUX selectively connects the output from one of the N DACS to an output of the MUX;
• the MUX comprises 4N MUX sub-circuits;
• and
• each of the MUX sub-circuits comprises first and second current paths from an input of the MUX to an output of the MUX;
• and
• wherein, for each of the 4N MUX sub-circuits:
• the first current path comprises a first inductor and a first switch;
• the second current path comprises a second inductor and a second switch;
• the first inductor is part of an output LC transmission line of the MUX sub-circuit;
• the second inductor is part of an input LC transmission line of the MUX sub-circuit;
• and
• the first and second inductors are sized such that parasitic capacitances of the first and second switches are substantially absorbed by the input and output LC transmission lines.

A circuit comprising:

• a 1:N demultiplexer (DEMUX);
• and
• N analog-to-digital converters (ADCs), each having an input that is connected to an output of the DEMUX,
• wherein:
• the DEMUX selectively connects in input of the DEMUX to one of the N ADCs;
• the DEMUX comprises 4N DEMUX sub-circuits;
• and
• each 4N DEMUX sub-circuits comprises first and second current paths from an input of the DEMUX to the outputs of the DEMUX;
• and
• wherein, for each of the 4N DEMUX sub-circuits:
• the first current path comprises a first inductor and a first switch;
• the second current path comprises a second inductor and a second switch;
• the first inductor is part of an output LC transmission line of the DEMUX sub-circuit;
• the second inductor is part of an input LC transmission line of the DEMUX sub-circuit;
• and
• the first and second inductors are sized such that parasitic capacitances of the first and second switches are substantially absorbed by the input and output LC transmission lines.