Data multiplexer single phase flip-flop
AssigneeIntel Corporation
InventorsChinmay Joshi, Dinesh Somasekhar
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Abstract
A single-phase clocked data multiplexer (MUX-D) scan capable flipflop (FF) design that improves over existing transmission-gate (t-gate) based master-slave flipflops in terms of dynamic capacitance (Cdyn) as well as performance while remaining comparable in area. Unique features of the design are a complementary metal oxide semiconductor (non-t-gate) style structure with an improvement in circuit parameters achieved by eliminating clock inversions and maximally sharing NMOS devices across NAND structures. The core of the flipflop adopts an all CMOS NAND, And-OR-Inverter (AOI) complex logic structure to implement a true edge-triggered flip-flop functionality.
Claims20
An apparatus comprising:
- a complex gate comprising an AND-OR-AND-INVERT logic gate to receive a data input and a scan input;
- and
- a plurality of NAND logic gates with shared n-type devices, wherein at least two NAND logic gates of the plurality of NAND logic gates is coupled to the complex gate, wherein the plurality of NAND logic gates includes a NAND gate to generate an output which is a sampled version of the data input or the scan input.
An apparatus comprising:
- a complex gate to receive a data input and a scan input;
- and
- a plurality of NAND logic gates with shared n-type devices, wherein at least some of the plurality of NAND logic gates are connected as set-reset latches, wherein at least one NAND gate of the plurality of NAND logic gates is coupled to an output of the complex gate.
A system comprising:
- a memory to store one or more instructions;
- a processor circuitry to execute the one or more instructions, wherein the processor circuitry is coupled to the memory;
- and
- a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes a flip-flop which comprises:
- a complex gate comprising an AND-OR-AND-INVERT logic gate to receive a data input and a scan input;
- and
- a plurality of NAND logic gates with shared n-type devices, wherein at least two NAND logic gates of the plurality of NAND logic gates is coupled to the complex gate, wherein the plurality of NAND logic gates includes a NAND gate to generate an output which is a sampled version of the data input or the scan input.
Dependencies are inferred from the claim text.