Semiconductor device for power amplification

A semiconductor device for power amplification comprising:

• a substrate;
• a first nitride semiconductor layer disposed above the substrate;
• a second nitride semiconductor layer disposed above the first nitride semiconductor layer, the second nitride semiconductor layer having a band gap larger than a band gap of the first nitride semiconductor layer;
• a first insulating layer disposed above the second nitride semiconductor layer;
• a source electrode and a drain electrode each disposed above the second nitride semiconductor layer, the source electrode and the drain electrode being spaced apart from each other;
• a gate electrode that is disposed between the source electrode and the drain electrode, and includes a gate field plate above an uppermost surface of the first insulating layer, the gate electrode forming a Schottky junction with an upper surface of the second nitride semiconductor layer through a first opening provided in the first insulating layer;
• a first source field plate disposed above the second nitride semiconductor layer between the gate electrode and the drain electrode, the first source field plate having a same potential as a potential of the source electrode;
• a second source field plate between the first source field plate and the drain electrode, the second source field plate having a same potential as the potential of the source electrode;
• and
• a metal layer above the second source field plate, the metal layer having electrical resistivity lower than electrical resistivity of the second source field plate,
• wherein, in a height-position relationship in a first direction that is a direction perpendicular to an upper surface of the substrate,
• the first source field plate includes a gate-electrode-facing side surface which includes at least a portion facing a side surface of the gate electrode close to the drain electrode at an identical height position,
• the gate-electrode-facing side surface includes a gate-electrode-closest-facing side surface that is a side surface including a closest point at which a distance from the side surface of the gate electrode close to the drain electrode is smallest in a plan view of the substrate, wherein an uppermost-edge position of the gate-electrode-closest-facing side surface is lower than a position of an uppermost surface of the gate electrode,
• a position of a lowermost surface of the first source field plate is above an outermost edge position of a lower surface of the gate filed field plate, the outermost edge portion being closest to the drain electrode, the lower surface of the gate field plate being in direct contact with the uppermost surface of the first insulating layer,
• in the first direction, an upper surface of the second source field plate is located above an upper surface of the first source field plate,
• in the first direction, a lower surface of the second source field plate is located above the lowermost surface of the first source field plate, and
• the metal layer is not provided directly above the first source field plate.