Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsTakanori Akashige, Kazunori Yamane
Life of this patent
Estimating the term…
Abstract
In a semiconductor device, an arithmetic circuit of a chip on a first stage performs a predetermined arithmetic operation on an input N-bit (N=4) selection signal. Similarly, an arithmetic circuit of each of chips on second and subsequent stages among chips on a total of M stages (M>N≥2, M=16) performs a predetermined common arithmetic operation on an operation result of the arithmetic circuit of the chip on the preceding stage. A determination circuit provided in each chip performs a predetermined common logic operation on a bit string of the N-bit signal, which is the operation result of the corresponding arithmetic circuit, thereby determining whether it is the chip selected by the selection signal.
Claims11
A semiconductor device comprising:
- cascaded modules on M stages, each of the modules including an arithmetic circuit and a determination circuit;
- and
- an interface circuit configured to input an N-bit selection signal (M>N≥2) for selecting any of the modules on the M stages to the arithmetic circuit of the module on a first stage,
- wherein the arithmetic circuit of the module on the first stage performs an N-bit arithmetic operation on the N-bit selection signal,
- wherein the arithmetic circuit of each of the modules on second to Mth stages performs the same N-bit arithmetic operation as that of the arithmetic circuit of the module on the first stage on an N-bit signal which is an operation result of the arithmetic circuit of the module on a preceding stage, and operation results of the respective arithmetic circuits of the modules on the M stages are different from each other, and
- wherein, in each of the modules on the M stages, the determination circuit receives an input of the N-bit signal which is the operation result of the arithmetic circuit, and determines whether a bit string of the input N-bit signal matches a specific bit string commonly determined for the modules on the M stages.
A semiconductor device comprising:
- cascaded modules on M stages,
- wherein each of the modules from a first stage to an (M−1)th stage includes an arithmetic circuit, and
- wherein each of the modules on the M stages includes a determination circuit,
- the semiconductor device further comprising:
- an interface circuit configured to input an N-bit selection signal (M>N≥2) for selecting any of the modules on the M stages to the arithmetic circuit and the determination circuit of the module on the first stage,
- wherein the arithmetic circuit of the module on the first stage performs an N-bit arithmetic operation on the input N-bit selection signal,
- wherein the arithmetic circuit of each of the modules from second to (M−1)th stages performs the same N-bit arithmetic operation as that of the arithmetic circuit of the module on the first stage on an N-bit signal which is an operation result of the arithmetic circuit of the module on a preceding stage, and operation results of the arithmetic circuits of the respective modules are different from each other,
- wherein the determination circuit of the module on the first stage determines whether a bit string of the input N-bit selection signal matches a specific bit string, and
- wherein the determination circuit of each of the modules on second to Mth stages receives an input of the N-bit signal which is an operation result of the arithmetic circuit of the module on the preceding stage, and determines whether a bit string of the input N-bit signal matches the specific bit string.
Dependencies are inferred from the claim text.