Enabling hierarchical data loading in a resistive processing unit (RPU) array for reduced communication cost

A method for training a computer-implemented neural network, comprising:

• providing an electronic circuit, comprising:
• a plurality of word lines;
• a plurality of bit lines intersecting said plurality of word lines at a plurality of grid points;
• a plurality of resistive processing units located at said plurality of grid points;
• a plurality of baseline stochastic pulse input units coupled to said plurality of word lines;
• a plurality of differential stochastic pulse input units coupled to said plurality of word lines;
• a plurality of bitline stochastic pulse input units coupled to said plurality of bit lines;
• and
• control circuitry coupled to said plurality of baseline pulse input units, said plurality of differential pulse input units, and said plurality of bitline stochastic pulse input units;
• and
• with said control circuitry, causing each of said baseline stochastic pulse input units to generate a baseline pulse train using base input data, each of the differential stochastic pulse input units to generate a differential pulse train using differential input data defining differences from said base input data, and each of said bitline stochastic pulse input units to generate a bitline pulse train using bit line input data.

A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of an apparatus, wherein said HDL design structure comprises:

• a plurality of word lines;
• a plurality of bit lines intersecting said plurality of word lines at a plurality of grid points;
• a plurality of resistive processing units located at said plurality of grid points;
• a plurality of baseline stochastic pulse input units coupled to said plurality of word lines;
• a plurality of differential stochastic pulse input units coupled to said plurality of word lines;
• a plurality of bitline stochastic pulse input units coupled to said plurality of bit lines;
• and
• control circuitry coupled to said plurality of baseline stochastic pulse input units, said plurality of differential stochastic pulse input units, and said plurality of bitline stochastic pulse input units and configured to cause each of said baseline stochastic pulse input units to generate a baseline pulse train using base input data, each of the differential stochastic pulse input units to generate a differential pulse train using differential input data defining differences from said base input data, and each of said bitline stochastic pulse input units to generate a bitline pulse train using bitline input data.