Reconfigurable cache hierarchy framework for the storage of FPGA bitstreams

A network-based apparatus comprising:

• at least one processor;
• and
• at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the network apparatus to
• configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device, and
• dynamically update pointers for the bitstreams at runtime based on changes to dynamic characteristics of the bitstreams, a pointer for a bitstream, among the pointers for the bitstreams, being based on at least one static characteristic and at least one dynamic characteristic, among the dynamic characteristics, the at least one dynamic characteristic including a frequency of request of the bitstream, and the at least one static characteristic including at least one of FPGA model, bitstream producer or shell type for the bitstream.