Driving amplifier stage with low output impedance
AssigneeQorvo US, Inc.
InventorsBaker Scott, George Maxim, Marcus Granger-Jones
Life of this patent
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Abstract
A driving amplifier with low output impedance is disclosed. In one aspect, a driving amplifier stage that does not need an inter-stage impedance matching network between the driving amplifier stage and an output amplifier stage in a transmission chain may be achieved by providing stacking transconductance devices within the driving amplifier stage and reusing a supply current to provide an intermediate signal with high current but moderated voltage swing to drive the output amplifier stage. In specifically contemplated aspects, the stacked transconductance devices may be complementary metal oxide semiconductor (CMOS) field effect transistors (FETs).
Claims20
A driving amplifier stage comprising:
- an input;
- an output;
- and
- an amplifier stack coupled to the input comprising:
- a first amplifier coupled to the input and the output;
- a second amplifier coupled to the input and coupled to the output such that a summed output signal is available at the output;
- a voltage supply input;
- and
- a mid-level voltage supply input node between the first amplifier and the second amplifier, wherein the mid-level voltage supply input node is configured to be held at a fraction of a voltage supply level to limit voltage swing across the first amplifier.
A driving amplifier stage comprising:
- an input configured to receive a radio frequency (RF) input;
- and
- an amplifier stack comprising:
- a first amplifier comprising a complementary metal oxide semiconductor (CMOS) arrangement of a first n-type field effect transistor (FET) (NFET) and a first p-type FET (PFET);
- a mid-level voltage supply input node coupled to the first amplifier and a second amplifier, wherein the mid-level voltage supply input node is configured to be held at a fraction of a voltage supply level to limit voltage swing across the first amplifier;
- the second amplifier comprising a CMOS arrangement of a second NFET and a second PFET, the second PFET coupled to the mid-level voltage supply input node, wherein the first amplifier and the second amplifier share a current;
- and
- an output configured to provide a summed output signal from the first amplifier and the second amplifier.
An amplifier system comprising:
- a driving amplifier stage comprising:
- an input configured to receive a radio frequency (RF) input;
- and
- an amplifier stack comprising:
- a first amplifier comprising a complementary metal oxide semiconductor (CMOS) arrangement of a first n-type field effect transistor (FET) (NFET) and a first p-type FET (PFET);
- a mid-level voltage supply input node coupled to the first amplifier and a second amplifier, wherein the mid-level voltage supply input node is configured to be held at a fraction of a voltage supply level to limit voltage swing across the first amplifier;
- the second amplifier comprising a CMOS arrangement of a second NFET and a second PFET, the second PFET coupled to the mid-level voltage supply input node, wherein the first amplifier and the second amplifier share a current;
- and
- an output configured to provide a summed output signal from the first amplifier and the second amplifier;
- and
- an output power amplifier stage coupled to the output.
Dependencies are inferred from the claim text.