High-speed, low distortion receiver circuit
AssigneeMacronix International Co., Ltd.
InventorsShang-Chi Yang, Jhen-Sheng Chih
Life of this patent
Estimating the term…
Abstract
A receiver circuit has a first stage circuit having a first stage input and a first stage output, the first stage output setting a first stage common mode voltage; a second stage circuit having a second stage input connected to the first stage output, and a second stage output setting a second stage common mode voltage; and a buffer circuit having a trip point voltage, connected to the second stage output. The first stage circuit can include circuit elements configured to establish the first stage common mode voltage so that the second stage common mode voltage matches the trip point voltage. The second stage circuit can include a self-biased amplifier.
Claims20
A receiver circuit, comprising:
- a first stage circuit having a first stage input and a first stage output, the first stage output setting a first stage common mode voltage;
- a second stage circuit having a second stage input connected to the first stage output, and a second stage output setting a second stage common mode voltage;
- and
- a buffer circuit having a trip point voltage, connected to the second stage output;
- wherein the first stage circuit includes circuit elements configured to set the first stage common mode voltage so that the second stage common mode voltage matches the trip point voltage.
A receiver circuit, comprising:
- a first differential pair of transistors, having drains connected through first and second matching resistors to a first drain-side supply voltage node, and sources connected to a current source transistor, a first transistor in the first differential pair having a gate connected to a reference voltage, and a second transistor in the first differential pair having a gate connected to a first stage input, drains of the first differential pair of transistors providing a differential pair of signals as a first stage output;
- a reference current circuit connected to the first drain-side supply voltage node, and comprising a reference resistor, a first transistor and a second transistor in series, the first transistor of the reference current circuit having a gate connected to the reference voltage, the second transistor of the reference current circuit having a gate connected to (i) a node between the reference resistor and the first transistor of the reference current circuit, and (ii) a gate of the current source transistor connected to the first differential pair of transistors;
- a second differential pair of transistors, having drains connected through first and second current mirror transistors to a second drain-side supply voltage node, having gates connected to respective ones of the differential pair of signals, and having sources connected to a second current source transistor;
- and
- a buffer circuit connected to the drain of one of the second differential pair of transistors.
A data receiver, comprising:
- a first amplifier circuit configured to receive a reference voltage and a first stage input signal, and to output control voltages based on the reference voltage and the first stage input signal;
- and
- a self-biased amplifier circuit configured to receive the control voltages from the first amplifier circuit, to set a self-bias voltage and to provide an output signal, wherein the self-bias voltage is connected to a current mirror of the self-biased amplifier circuit.
Dependencies are inferred from the claim text.