IC including standard cells and SRAM cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
Estimating the term…
Abstract
An IC is provided. The IC includes a first P-type FinFET and a second P-type FinFET. The first P-type FinFET includes a silicon germanium channel region. The second P-type FinFET includes a Si channel region. First source/drain regions of the first P-type FinFET are formed on a discontinuous semiconductor fin, and second source/drain regions of the second P-type FinFET are formed on a continuous semiconductor fin. A first depth of the first source/drain regions is different from a second depth of the second source/drain regions.
Claims20
An integrated circuit (IC), comprising:
- a first P-type FinFET comprising a silicon germanium channel region;
- and
- a second P-type FinFET comprising a Si channel region,
- wherein first source/drain regions of the first P-type FinFET are formed on a discontinuous semiconductor fin, and second source/drain regions of the second P-type FinFET are formed on a continuous semiconductor fin,
- wherein a first depth of the first source/drain regions is different from a second depth of the second source/drain regions.
An integrated circuit (IC), comprising:
- a logic array comprising a plurality of logic cells arranged in rows and columns, wherein each of the logic cells comprises at least one first P-type fin field-effect transistor (FinFET);
- and
- a memory array comprising a plurality of memory cells arranged in rows and columns, wherein each of the memory cells comprises at least one second P-type FinFET,
- wherein the first P-type FinFETs of the logic cells arranged in the same column of the logic array share a continuous semiconductor fin, and the continuous semiconductor fin of the first P-type FinFETs and a discontinuous semiconductor fin of the second P-type FinFET of each of the memory cells comprise different materials,
- wherein source/drain regions of the second P-type FinFET are shallower than source/drain regions of the first P-type FinFET.
An integrated circuit (IC), comprising:
- a plurality of first cells arranged in a first column, wherein each of the first cells comprises a plurality of first P-type fin field-effect transistors (FinFETs);
- and
- a plurality of second cells arranged in a second column, wherein each of the second cells comprises a plurality of second P-type FinFETs,
- wherein the first P-type FinFETs of each of the first cells share a first continuous semiconductor fin, and the second P-type FinFETs of the second cells share a second continuous semiconductor fin,
- wherein the first and second continuous semiconductor fins are formed by different materials, and
- wherein source/drain regions of the second P-type FinFETs and source/drain regions of the first P-type FinFETs have different depths.
Dependencies are inferred from the claim text.