Concurrent memory access operations
AssigneeArm Limited
InventorsLalit Gupta, Bo Zheng, Fakhruddin Ali Bohra, Nimish Sharma, Nicolaas Klarinus Johannes Van Winkelhoff, El Mehdi Boujamaa
Life of this patent
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Abstract
Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.
Claims22
A method, comprising:
- providing memory with one or more banks;
- coupling read-write column multiplexer circuitry to the memory via bitlines including coupling one or more write column multiplexers to a write driver via one or more first shared bitlines for write operations and coupling two or more read column multiplexers to a sense amplifier via one or more second shared bitlines for read operations;
- and
- performing concurrent read operations and write operations in the one or more banks of the memory with the one or more write column multiplexers and the two or more read column multiplexers via the one or more first shared bitlines and the one or more second shared bitlines.
A device, comprising:
- memory architecture having a plurality of bitcell arrays;
- column multiplexer circuitry coupled to the memory architecture via a plurality of bitlines including one or more write column multiplexers coupled to a write driver via one or more first the shared bitlines for write operations and two or more-a plurality of read column multiplexers coupled to a sense amplifier via one or more second shared bitlines for read operations;
- logic circuitry that performs concurrent memory access operations in the plurality of bitcell arrays of the memory architecture with the one or more write column multiplexers and the two or more read column multiplexers via the one or more first shared bitlines and the one or more second shared bitlines;
- and
- timing circuitry having one or more latches that are arranged to avoid data-to-bitline coupling between the plurality of bitlines while performing the concurrent memory access operations in the plurality of bitcell arrays of the memory architecture.
A system, comprising:
- a processor;
- and
- memory having stored thereon instructions that, when executed by the processor, cause the processor to:
- access memory having a plurality of banks;
- couple column multiplexer circuitry to the memory with bitlines including coupling one or more write column multiplexers to a write driver via one or more first shared bitlines for write operations and coupling two or more read column multiplexers to a sense amplifier via one or more second shared bitlines for read operations;
- and
- perform concurrent read-write access operations in the plurality of banks of the memory with the one or more write column multiplexers and the two or more read column multiplexers via the one or more first shared bitlines and the one or more second shared bitlines.
Dependencies are inferred from the claim text.