Printed circuit board with integrated fusing and arc suppression
AssigneeEaton Intelligent Power Limited
InventorsKaijam M. Woodley, Michael K. Balck, Matthew J. Koebert
Life of this patent
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Abstract
A circuit board with integrated fusing includes an insulating substrate having a circuit trace formed on a surface thereof, the circuit trace including a first circuit trace portion and a second circuit trace portion. A fusible link electrically connects the first circuit trace portion to the second circuit trace portion, the fusible link including a planar surface extending from the first circuit trace portion to the second circuit trace portion. A dielectric reflow encapsulates the fusible link on the planar surface from the first circuit trace portion to the second circuit trace portion.
Claims20
A method comprising:
- providing an electrically insulating substrate having a conductive trace substrate on a first surface thereof;
- etching the conductive trace substrate to form a circuit trace with a plurality of fusible links in the circuit trace, each of the plurality of fusible links comprising a portion of the circuit trace having a reduced cross-sectional area from a first end to a second end of the respective fusible link, wherein a portion of the circuit trace comprises a plurality of non-linear segments containing the plurality of fusible links;
- applying a dielectric on the circuit trace so as to encapsulate each of the fusible links from the first end to the second end, wherein the dielectric encapsulates an area of the electrically insulating substrate containing the plurality of non-linear segments;
- and
- forming a plurality of isolation gaps in the electrically insulating substrate, the plurality of isolation gaps including isolation gaps that surround the plurality of non-linear segments and isolation gaps positioned to separate each of the plurality of non-linear segments from one another, with the dielectric formed down into the plurality of isolation gaps.
A method comprising:
- etching a conductive trace substrate on an electrically insulating substrate to form a circuit trace comprising:
- non-linear segments arranged adjacent to one and other;
- and one or more fusible links in the circuit trace, each of the one or more fusible links configured to open in response to receiving an electrical overage;
- encapsulating each of the one or more fusible links with a dielectric encapsulant configured to prevent open circuit arcing by reflow into a respective open fusible link;
- and
- forming isolation gaps in the electrically insulating substrate, the isolation gaps surrounding the non-linear segments such that each non-linear segment is separated from the other non-linear segments.
A method comprising:
- forming an isolation region on an electrically insulating substrate, the isolation region comprising openings in the electrically insulating substrate;
- etching a conductive trace substrate to form a circuit trace in the isolation region, the circuit trace comprising:
- adjacent spiral paths into and out of a center of the isolation region, each spiral path being separated by one or more of the openings in the electrically insulating substrate;
- and one or more fusible links in the circuit trace configured to open in response to receiving an electrical overage;
- and
- encapsulating each of the one or more fusible links with a dielectric encapsulant configured to prevent open circuit arcing by reflow into a respective open fusible link.
Dependencies are inferred from the claim text.