Registration and mode switching for devices in a distributed audio system

A switchable part device in an audio system, the switchable part device comprising:

• a processor;
• a first memory storing instructions associated with a first operating mode;
• a second memory storing instructions associated with a second operating mode;
• and
• a field-programmable gate array (FPGA) configured to switch operation of the switchable part device between the first operating mode and the second operating mode by switching select signals corresponding to the first and second memory, the FPGA further configured to start a reset timer and assert an associated timer signal to the processor, and release the associated timer signal responsive to the reset timer reaching a threshold time interval.

A distributed audio system comprising:

• a switchable part device in an audio system, the switchable part device comprising:
• a processor;
• a first memory storing instructions associated with a first operating mode;
• a second memory storing instructions associated with a second operating mode;
• and
• a field-programmable gate array (FPGA) configured to switch operation of the switchable part device between the first operating mode and the second operating mode by switching select signals corresponding to the first and second memory, the FPGA further configured to start a reset timer and assert an associated timer signal to the processor, and release the associated timer signal responsive to the reset timer reaching a threshold time interval,
• wherein the first memory or the second memory further stores instructions executable by the process to enter a registration mode for performing a Digital Enhanced Cordless Telecommunications (DECT) registration of a portable device responsive to a single button press received at the portable device or responsive to receiving a registration signal from a charging cradle for the portable device.