Input dependent common mode biasing

A circuit comprising:

• a first capacitor having first and second terminals;
• a second capacitor having first and second terminals, the second terminals of the first and second capacitors are coupled together, and the circuit is configured to receive an input voltage and a common mode input bias voltage at the first terminal of the first capacitor and to receive a reference voltage at the first terminal of the second capacitor;
• a voltage generator circuit having an output coupled to the second terminals of the first and second capacitors, wherein the voltage generator circuit is configured to provide a common mode output bias voltage at the second terminals of the first and second capacitors, and the common mode output bias voltage is based on the common mode input bias voltage;
• an analog-to-digital converter (ADC) having a first stage that includes a switched capacitor circuit and the voltage generator circuit;
• and
• a multiplexer having battery voltage inputs and a multiplexer output, wherein the multiplexer output is coupled to an input of the ADC.

A system comprising:

• first and second battery cells;
• a multiplexer having multiplexer inputs coupled to the first and second battery cells, and having multiplexer outputs;
• and
• an analog-to-digital converter (ADC) including:
• a switched capacitor circuit including:
• a first capacitor having first and second terminals;
• first and second switches coupled between the multiplexer outputs and the first terminal of the first capacitor;
• third and fourth switches;
• a second capacitor having a first terminal coupled to the third and fourth switches and having a second terminal coupled to the second terminal of the first capacitor;
• a fifth switch having a first terminal coupled to the second terminals of the first and second capacitors, and having a second terminal;
• and
• a sixth switch having first and second terminals, wherein the first terminal is coupled to the first terminal of the fifth switch and coupled to the second terminals of the first and second capacitors;
• an integrator circuit including:
• an operational amplifier (op-amp) having an input and an output, the input of the op-amp coupled to the second terminal of the fifth switch;
• and
• a third capacitor coupled between the input and the output of the op-amp;
• and
• a voltage generator circuit having a generator output coupled to the second terminal of the sixth switch, the voltage generator circuit configured to provide a common mode output bias voltage at the second terminal of the sixth switch responsive to a common mode input bias voltage at a terminal of the first switch.