Dynamically doped field-effect transistor and a method for controlling such

A method for controlling a device comprising a field-effect transistor and a controller, the field effect transistor comprising:

• a semiconductor layer;
• a source terminal, a drain terminal and a single gate terminal, the single gate terminal being connected to a gate comprising at least a first gate portion;
• wherein the source and drain terminals are arranged on a first side of the semiconductor layer and the first gate portion is arranged on a second side of the semiconductor layer opposite the first side;
• wherein the semiconductor layer comprises a source region along which the source terminal abuts the semiconductor layer and a drain region along which the drain terminal abuts the semiconductor layer;
• wherein the first gate portion and the source terminal are arranged to overlap with a first common region of the semiconductor layer and the first gate portion and the drain terminal are arranged to overlap with a second common region of the semiconductor layer, the first common region forming a sub-region of the source region and the second common region forming a sub-region of the drain region, wherein the source region further comprises a first gap region which the first gate portion does not overlap and the drain region further comprises a second gap region which the first gate portion does not overlap;
• the controller being configured to switch the field-effect transistor to an active state by applying a voltage to the gate, the applied voltage in the active state inducing an electrostatic doping of the first common region and the second common region of the semiconductor layer and inducing a channel in a channel region of the semiconductor layer, wherein the channel region extends between the first common region and the second common region;
• and
• switch the field-effect transistor to an inactive state by applying a voltage to the gate, the applied voltage in the inactive state reducing an amount of electrostatic doping of the first common region and the second common region of the semiconductor layer and stopping inducing the channel in the channel region of the semiconductor layer;
• wherein the first common region and the second common region have a respective first doping level when the field-effect transistor is in the inactive state, and a respective electrostatically increased second doping level when the field-effect transistor is in the active state;
• and
• wherein the respective first doping level is lower than a chemical or an intrinsic doping level of the semiconductor layer before addition of the source terminal, the drain terminal and the single gate terminal to the semiconductor layer;
• the method comprising switching the field-effect transistor to an active state by controlling a voltage of the gate, which induces an electrostatic doping of the first common region and the second common region of the semiconductor layer and induces a channel in a channel region of the semiconductor layer, extending between the first common region and the second common region.

A device arrangement comprising:

• a first device comprising a first field-effect transistor and a first controller, and a second device comprising a second field-effect transistor and a second controller, each of the field effect transistors comprising:
• a semiconductor layer;
• a source terminal, a drain terminal and a single gate terminal, the single gate terminal being connected to a gate comprising at least a first gate portion;
• wherein the source and drain terminals are arranged on a first side of the semiconductor layer and the first gate portion is arranged on a second side of the semiconductor layer opposite the first side;
• wherein the semiconductor layer comprises a source region along which the source terminal abuts the semiconductor layer and a drain region along which the drain terminal abuts the semiconductor layer;
• wherein the first gate portion and the source terminal are arranged to overlap with a first common region of the semiconductor layer and the first gate portion and the drain terminal are arranged to overlap with a second common region of the semiconductor layer, the first common region forming a sub-region of the source region and the second common region forming a sub-region of the drain region, wherein the source region further comprises a first gap region which the first gate portion does not overlap and the drain region further comprises a second gap region which the first gate portion does not overlap;
• each controller individually configured to switch the corresponding field-effect transistor to an active state by applying a voltage to the gate, the applied voltage in the active state inducing an electrostatic doping of the first common region and the second common region of the semiconductor layer and inducing a channel in a channel region of the semiconductor layer, wherein the channel region extends between the first common region and the second common region;
• and switch the field-effect transistor to an inactive state by applying a voltage to the gate, the applied voltage in the inactive state reducing an amount of electrostatic doping of the first common region and the second common region of the semiconductor layer and stopping inducing the channel in the channel region of the semiconductor layer;
• wherein the first common region and the second common region have a respective first doping level when the field-effect transistor is in the inactive state, and a respective second doping level which is electrostatically increased relative to the respective first doping level when the field-effect transistor is in the active state;
• and
• wherein the respective first doping level is lower than a chemical or an intrinsic doping level of the semiconductor layer before addition of the source terminal, the drain terminal and the single gate terminal to the semiconductor layer;
• wherein the semiconductor layer of the first field-effect transistor is the same as the semiconductor layer of the second field-effect transistor;
• wherein the first gap region of the second field-effect transistor is adjacent the first gap region or the second gap region of the first field-effect transistor;
• and
• wherein the gate of the first field-effect transistor and the gate of the second field-effect transistor are configured to be individually controlled.