Cell structure and its related semiconductor device

A cell structure of a semiconductor device, comprising:

• a semiconductor substrate of a first conductivity type;
• a plurality of trench units, arranged in said semiconductor substrate at a first side, wherein said plurality of trench units comprise at least two first trench units and at least one second trench unit, and said first trench units are arranged separately, and said second trench units are disposed on two outer sides of said first trench unit;
• a first gate region, arranged in said first trench unit and isolated from said semiconductor substrate by a first dielectric;
• a second gate region, arranged in said second trench unit and isolated from said semiconductor substrate by a second dielectric;
• a carrier barrier region of said first conductivity type, arranged adjacent to the bottom portion of said first trench unit;
• an electric field shielding region of a second conductivity type, arranged adjacent to the bottom portion of said second trench unit;
• a source-body region of said second conductivity type, arranged between two said first trench units, wherein said source-body region comprises more than one source region of said first conductivity type, and said source region is in contact with said first dielectric of said first trench unit, and said source-body region and said source region are located in the surface region of said semiconductor substrate at said first side;
• a floating region, arranged between said first trench unit and said second trench unit;
• a first metal layer, disposed on a top portion of said semiconductor substrate at said first side, wherein said first metal layer is in contact with said source-body region, and isolated from said floating region and some or all of said first trench units by a third dielectric;
• a first semiconductor region, implemented in said semiconductor substrate at a second side, wherein said second side is opposite to said first side;
• and
• a second metal layer, disposed on surface of said semiconductor substrate at said second side and in contact with said first semiconductor region,
• wherein a plurality of said second trench units are provided on an outer side of said first trench unit, and said electric field shielding region of said second conductivity type is provided adjacent to bottom of each of said second trench units,
• wherein more than one third trench unit is provided between said plurality of second trench units, said structure of said third trench unit is the same with said structure of said first trench unit, and said first gate region of at least one of said third trench units is connected to said first metal layer.