Arrayed switch circuit, switching element and system chip package structure

An arrayed switch circuit comprising:

• a substrate;
• a plurality of signal conductive pads disposed on the substrate at intervals, wherein the plurality of signal conductive pads are arranged on the substrate to form a signal conductive pad array, each of the plurality of signal conductive pads has a row position and a column position in the signal conductive pad array, a row signal switch is provided between any two adjacent signal conductive pads corresponding to the same row position, and a column signal switch is provided between any two adjacent signal conductive pads corresponding to the same column position;
• a plurality of signal expansion pins connected to the signal conductive pads located on at least one side of the signal conductive pad array through a plurality of signal expansion switches respectively, and
• a plurality of power conductive pads and a plurality of power expansion pins, wherein the plurality of power conductive pads are disposed on the substrate at intervals and arranged on the substrate to form an power conductive pad array, each of the plurality of power conductive pads has a row position and a column position in the power conductive pad array, a row power switch is provided between any two adjacent power conductive pads corresponding to the same row position, a column power switch is provided between any two adjacent power conductive pads corresponding to the same column position, and the plurality of power expansion pins are disposed on the substrate at intervals and connected to the plurality of power conductive pads located on one side of the power conductive pad array through a plurality of power expansion switches respectively.