Data path circuit and method

A method comprising:

• receiving a first read command;
• sensing first data from a memory array based on the first read command;
• providing the sensed first data to a first data bus;
• asserting a first latch signal a time after receiving the first read command;
• latching the sensed first data from the first data bus into one latch circuit of N latch circuits in response to the assertion of the first latch signal, wherein the N latch circuits are coupled in parallel, wherein each latch circuit of the N latch circuits has data inputs coupled to the first data bus, and wherein N is a positive integer greater than or equal to 2;
• causing an output of the one latch circuit to propagate to a data input of a logic circuit via a data path;
• asserting an output latch signal a first time after receiving the first read command to latch the sensed first data from the one latch circuit into the logic circuit;
• receiving a second read command;
• sensing second data from the memory array based on the second read command;
• selecting a next latch circuit from the N latch circuits;
• latching the sensed second data into the next latch circuit;
• causing an output of the next latch circuit to propagate to the data input of the logic circuit via the data path;
• and
• asserting the output latch signal a second time after receiving the second read command to latch the sensed second data from the next latch circuit into the logic circuit.

A memory circuit comprising:

• a memory array configured to provide read data to a first data bus;
• a controller configured to receive a read command and a clock signal and assert an output latch signal a predetermined number of clock pulses of the clock signal after reception of the read command, the controller further configured to provide a memory address to the memory array based on the read command;
• a read control circuit configured to, in response to the read command,
• assert a first read signal to cause the memory array to provide read data to the first data bus based on the memory address, and,
• a fixed time after asserting the first read signal, assert a first latch signal, wherein the fixed time is asynchronous with respect to the clock signal;
• N latch circuits coupled in parallel, wherein each latch circuit of the N latch circuits has data inputs coupled to the first data bus, and a latch input, wherein N is a positive integer greater than or equal to 2;
• a latch control circuit configured to receive the first latch signal from the read control circuit and provide a respective latching signal to the latch input of each latch circuit of the N latch circuits, wherein the latch control circuit is configured to cause the latching of data into one of the N latch circuits in response to the assertion of the first latch signal by asserting a respective output latch signals;
• a data multiplexer having a data output, N data inputs respectively coupled to data outputs of the N latch circuits, and a selection input, wherein the data multiplexer is configured to select a data input of the N data inputs of the data multiplexer to connect to the data output of the data multiplexer based on the selection input of the data multiplexer;
• a data path having a data input coupled to the data output of the data multiplexer;
• and
• a logic circuit having a data output, and a data input coupled to the data output of the data path, wherein the logic circuit is configured to latch data at the data input of the logic circuit when the output latch signal is asserted.