US 12,154,624 B2 · Differential programming of two-terminal memory with program detection and multi-path disablement

Abstract

Improved differential programming of multiple two-terminal memory cells that define an identifier bit is provided. Differential programming can apply a program cycle to multiple memory cells concurrently, detect a program event for one (or a first group) of the memory cells and disconnect all of the memory cells from a program supply voltage in response to detecting the program event. Moreover, disconnecting the memory cells can be accomplished prior to a duration of the program cycle, serving to mitigate an invalid data result for the identifier bit, as well as reduce power consumption associated with the differential programming. Circuits providing intrinsic suppression of a non-programmed memory cell(s) defining an identifier bit in response to programming of another memory cell (or group of cells) defining the identifier bit are included. Differential programming can reduce power consumption and mitigate or avoid invalid data results for an identifier bit.

Claims20

Dependent claims

A method for programming a plurality of two-terminal resistive switching memory devices that define an identifier bit, comprising:

connecting a first terminal of a first two-terminal resistive switching memory cell to a voltage source by way of a first switch;
connecting a first terminal of a second two-terminal resistive switching memory cell to the voltage source by way of a second switch, wherein the first two-terminal resistive switching memory cell and the second two-terminal resistive switching memory cell define an identifier bit;
connecting second terminals of the first two-terminal resistive switching memory cell and of the second two-terminal resistive switching memory cell to low voltage;
apply a program voltage at the voltage source for a duration of a program cycle;
detecting a program event for the first two-terminal resistive switching memory cell or for the second two-terminal resistive switching memory cell;
and
opening the first switch and opening the second switch to disconnect the first two-terminal resistive switching memory cell and the second two-terminal resistive switching memory cell from the voltage source in response to detecting the program event and before completing the duration of the program cycle.

4 more elements

An integrated circuit device, comprising:

an array of two-terminal resistive switching memory cells, the array further comprising:
a first two-terminal resistive switching memory cell having a first terminal and a second terminal;
a second two-terminal resistive switching memory cell having a first terminal and a second terminal;
a first bitline electrically connected to the first terminal of the first two-terminal resistive switching memory cell;
a second bitline electrically connected to the first terminal of the second two-terminal resistive switching memory cell;
a switching circuit electrically coupled to the second terminal of the second two-terminal resistive switching memory cell and to the second terminal of the first two-terminal resistive switching memory cell;
and
a wordline for selectively activating or deactivating the switching circuit;
a voltage source selectively coupled to the first bitline through a first transistor and to the second bitline through a second transistor;
a low voltage, or ground selectively coupled with the second terminal of the second two-terminal resistive switching memory cell and with the second terminal of the first two-terminal resistive switching memory cell in response to activation of the switching circuit by the wordline;
array control circuitry configured to detect a change in voltage on the first bitline or a change in voltage on the second bitline in comparison to a reference voltage;
and
an array controller, wherein the array controller is configured to:
define the first two-terminal resistive switching memory cell and the second two-terminal resistive switching memory cell as a single identifier bit;
implement a differential program for the single identifier bit;
detect a program event at the first bitline or at the second bitline utilizing the array control circuity in response to the differential program;
and
disconnect the first bitline and the second bitline from the voltage source in response to detecting the program event.

15 more elements

Dependencies are inferred from the claim text.

Differential programming of two-terminal memory with program detection and multi-path disablement

Life of this patent

Differential programming of two-terminal memory with program detection and multi-path disablement

Life of this patent

Abstract

Claims20